Method for forming controllable surface enhanced three dimension

Details Method for forming controllable surface enhanced three dimension Method for forming controllable surface enhanced three dimension

1997-06-25

1999-03-16

Dutton, Brian

Semiconductor device manufacturing: process

Making passive device

Stacked capacitor

H01L 2120

Patent

active

058829792

ABSTRACT:
An embodiment of the present invention develops a process for controlling the grain size of a Hemi-Spherical Grained (HSG) silicon film by the steps of: performing a controlled implant of impurities into an amorphous silicon film; providing silicon seeding sites onto the surface of the amorphous silicon film; heat treating the amorphous silicon film, impregnated with the impurities and its surface having silicon seeding sites thereon, to cause HSG formation The implanting of the impurities into the amorphous material is controlled to place the impurities at a desired depth to thereby control the grain size of the HSG silicon.

REFERENCES:
patent: 5385863 (1995-01-01), Tatsumi et al.
patent: 5486488 (1996-01-01), Kamiyama
patent: 5721171 (1998-02-01), Ping et al.

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