Semiconductor device manufacturing: process – Chemical etching – Vapor phase etching
Reexamination Certificate
2002-08-15
2004-07-20
Cuneo, Kamand (Department: 2829)
Semiconductor device manufacturing: process
Chemical etching
Vapor phase etching
C438S780000, C438S790000, C029S825000, C216S037000
Reexamination Certificate
active
06764957
ABSTRACT:
CROSS REFERENCE TO RELATED APPLICATIONS
This application claims the priority benefit of Taiwan application serial no. 91115387, filed Jul. 11, 2002.
BACKGROUND OF INVENTION
1. Field of Invention
The present invention relates to a method for fabricating a semiconductor device. More particularly, the present invention relates to a method for forming a contact or via plug with small dimensions by using multi-step etching.
2. Description of Related Art
In accompany with the advances of semiconductor technology, semiconductor devices are continuously miniaturized. In order to further increase the device integration in deep sub-micron VLSI techniques, multi-level metal interconnect structures containing more than two metal layers are required. In a multi-level metal interconnect process, two metal layers are electrically connected by via plugs formed in the isolating layer between them, wherein the via plugs are fabricated by forming openings in the isolating layer and filling the openings with metal.
In a method for forming a contact or via plug in the prior art, a dielectric layer is formed on a substrate having a first metal interconnect layer thereon. The dielectric layer is patterned to form an opening exposing the first metal interconnect layer, and then the opening is filled with metal to form a metal contact or via plug. Thereafter, a second metal interconnect layer is formed on the substrate contacting with the metal contact or via plug to electrically connect with the first metal interconnect layer.
As the integration of integrated circuits (IC) continuously gets higher, the metal interconnects and the metal via plugs are miniaturized correspondingly as well as the devices. However, it is hard to form a contact or via plug having a smaller bottom portion because of the restrictions imposed by lithography process and etching process. Meanwhile, filling metal into an opening having a high aspect ratio is usually a challenge.
SUMMARY OF INVENTION
Accordingly, this invention provides a method for forming a contact or via plug to break through the restrictions imposed by lithography process and etching process, so as to form a contact or via plug with a smaller bottom portion.
This invention also provides a method for forming a contact or via plug to solve the problem that a small contact/via hole with a high aspect ratio cannot be easily filled with metal.
In a method for forming a contact or via plug of this invention, a dielectric layer is formed on a substrate and then a patterned photoresist layer is formed on the dielectric layer. A portion of the dielectric layer exposed by the photoresist layer is removed to form a first opening with the photoresist layer as a mask. A first liner is then formed on the surfaces of the photoresist layer. The first liner comprises a material such as polymer and is formed with, for example, plasma-enhanced chemical vapor deposition (PECVD). A portion of the dielectric layer under the first opening is removed to form a second opening by using the first liner and the photoresist layer as a mask. The second opening incorporates the first opening, and the etching rate of the first liner is smaller than that of the dielectric layer in the etching process. A second liner is formed on the photoresist layer covering the first liner. The second liner comprises a material such as polymer and is formed with, for example, plasma-enhanced chemical vapor deposition (PECVD). A portion of the dielectric layer under the second opening is removed to form a third opening exposing the substrate by using the second liner and the photoresist layer as a mask. The third opening incorporates the second opening, and the etching rate of the second liner is smaller than that of the dielectric layer in the etching process. The second liner, the first liner and the photoresist layer are removed and then a conductive material is filled into the third opening to form a contact or via plug. The contact or via plug formed by using the multi-step etching method of this invention has a bottom width smaller than the top width thereof.
In another method for forming a contact or via plug of this invention, a dielectric layer is formed on a substrate and then a patterned photoresist layer is formed on the dielectric layer. A portion of the dielectric layer exposed by the photoresist layer is removed to form a first opening with the photoresist layer as a mask. Thereafter, the photoresist layer is removed and a first liner is formed on the dielectric layer and in the first opening. The first liner preferably comprises silicon nitride or a metal material. A portion of the dielectric layer under the first opening is removed to form a second opening by using the first liner as a mask. The second opening incorporates the first opening, and the etching rate of the first liner is smaller than that of the dielectric layer in the etching process. Thereafter, a second liner is formed on the substrate covering the first liner. The second liner preferably comprises silicon nitride or a metal material. A portion of the dielectric layer under the second opening is removed to form a third opening exposing the substrate by using the second liner as a mask. The third opening incorporates the second opening, and the etching rate of the second liner is smaller than that of the dielectric layer in the etching process. The second liner and the first liner are removed and then a conductive material is filled into the third opening to form a contact or via plug. The contact or via plug formed by using the multi-step etching method of this invention has a bottom width smaller than the top width thereof. Besides, it is also feasible to directly fill a conductive material into the third opening without removing the first liner and the second liner that comprises silicon nitride or metal. If the first and the second liners comprise silicon nitride, they are taken as a part of the dielectric layer. If the first and the second liners comprise metal, they are taken as a part of the contact or via plug.
Since a multi-step etching process is used to form a contact/via hole having a smaller bottom portion in the method for forming a contact or via plug of this invention, the restrictions imposed by current lithography and etching processes can be broken through.
Moreover, the contact/via hole formed by using the method of this invention has a top width larger than the bottom width thereof, so the metal (conductive material) can be easily filled into the contact/via hole.
Furthermore, since the contact or via plug formed by using the method of this invention has a wider top portion, the resistance of the contact or via plug can be reduced.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.
REFERENCES:
patent: 5915177 (1999-06-01), Tseng
patent: 6211092 (2001-04-01), Tang et al.
patent: 6235214 (2001-05-01), Deshmukh et al.
patent: 6277544 (2001-08-01), Singh et al.
patent: 6284149 (2001-09-01), Li et al.
patent: 6383941 (2002-05-01), Shen et al.
patent: 6573177 (2003-06-01), Liang et al.
patent: 6613686 (2003-09-01), Nishizawa
Cuneo Kamand
Jiang Chyun IP Office
Kilday Lisa
Macronix International Co. Ltd.
LandOfFree
Method for forming contact or via plug does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method for forming contact or via plug, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for forming contact or via plug will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3254290