Method for forming conductive lines and vias

Details Method for forming conductive lines and vias Method for forming conductive lines and vias

1982-07-22

1984-02-07

Newsome, John H.

Coating processes

Electrical product produced

Integrated circuit, printed circuit, or circuit board

427 88, H01L 2710

Patent

active

044303653

ABSTRACT:
A multilevel metallurgy is formed on a dielectric body, particularly a multilayer ceramic (MLC) body. The interconnection lines and via studs are formed as an integral structure from a blanket metal layer thus eliminating the interface between the via pad and via stud.

REFERENCES:
patent: 3605260 (1971-09-01), Spridco et al.
patent: 3726002 (1973-04-01), Greenstein et al.
patent: 3853715 (1974-12-01), Romankiw
patent: 3968193 (1976-07-01), Langston, Jr. et al.
patent: 4040891 (1977-08-01), Chang et al.
patent: 4045302 (1977-08-01), Gibbs et al.
patent: 4132586 (1979-01-01), Schaible et al.
patent: 4172004 (1979-10-01), Alcorn et al.
patent: 4184909 (1980-01-01), Chang et al.
patent: 4272561 (1981-06-01), Rothman et al.
IBM Technical Disclosure Bulletin, vol. 17, No. 6, Nov. 1974, "Monolithic Studs for Interlevel Connectors", V. Platter and G. C. Schwartz, pp. 1605-1606.
IBM Technical Disclosure Bulletin, vol. 19, No. 9, Feb. 1977, "Forming Planar Integrated Circuit Metallization", W. C. Metzger and P. M. Schaible, pp. 3364-3365.
IBM Technical Disclosure Bulletin, vol. 23, No. 4, Sep. 1980, "Reactive Ion Etch Process for Metal Wiring Using a Buried Mask", J. R. Kitcher, p. 1394.
IBM Technical Disclosure Bulletin, vol. 23, No. 4, Sep. 1980, "Integral Stud for Multilevel Metal", J. R. Kitcher, p. 1395.

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