Method for forming complementary patterns in a semiconductor mat

Details Method for forming complementary patterns in a semiconductor mat Method for forming complementary patterns in a semiconductor mat

1988-11-03

1990-09-11

Chaudhuri, Olik

Fishing, trapping, and vermin destroying

437962, 148DIG105, H01L 21265

Patent

active

049563068

ABSTRACT:
A semiconductor material is overlayed with sequentially stacked layers including a protective layer, an affinity layer having an affinity for a second implant blocking material comprising tungsten, a first implant blocking layer and a masking layer having a first pattern. A portion of the first blocking layer not being masked is removed to expose a first portion of the affinity layer and a first dopant is implanted into the underlying semiconductor through the exposed first portion of the affinity layer. The mask is removed to expose the first blocking layer and a second blocking layer is formed from the second blocking material over the exposed first portion of the affinity layer but not over the exposed first blocking layer. The first blocking layer is removed to expose a second portion of the affinity layer which constitutes a second pattern. A second dopant is implanted into the underlying semiconductor through the exposed second portion of the affinity layer. The first blocking layer may include silicon oxide, the second blocking layer may include tungsten and the affinity layer may include polysilicon.

REFERENCES:
patent: 4448800 (1984-05-01), Ehara et al.
patent: 4578859 (1986-04-01), Hause et al.
patent: 4584027 (1986-04-01), Metz, Jr. et al.
Brown et al., Selective CVD Tungsten Via Plugs for Multilevel Metallization, pp. 66-69, Technical Digest of the International Electron Devices Meeting (IEEE), Los Angeles, Calif., Dec. 7-10, 1986.

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