Method for forming capacitor using FET process and structure for

Details Method for forming capacitor using FET process and structure for Method for forming capacitor using FET process and structure for

1990-09-17

1991-09-03

Griffin, Donald A.

Electricity: electrical systems and devices

Electrostatic capacitors

Fixed capacitor

357 234, 437 43, H01G 406, H01L 2170

Patent

active

050459660

ABSTRACT:
A polysilicon or equivalent plate, to be used as an upper plate of the capacitor, is first formed over an oxide layer grown on a substrate. The length of the upper plate is made shorter than gate lengths of MOS transistors formed with the same process so that, after dopants are deposited into exposed regions of the substrate on both sides of the plate in a manner identical to forming self-aligned source and drain regions of an MOS transistor, the dopants will side-diffuse during drive-in and the diffused regions will be closely separated or merged under the plate. The resulting capacitor structure has a more stable capacitance with varying V.sub.GS levels than MOS transistors merely connected and used as capacitors and has a lower series resistance.

REFERENCES:
patent: 4931408 (1990-06-01), Hshieh
patent: 4956698 (1990-09-01), Wang
patent: 4957877 (1990-09-01), Tam et al.

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