Semiconductor device manufacturing: process – Making passive device – Trench capacitor
Reexamination Certificate
2000-01-27
2001-10-23
Bowers, Charles (Department: 2823)
Semiconductor device manufacturing: process
Making passive device
Trench capacitor
C438S386000, C438S387000
Reexamination Certificate
active
06306720
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATION
This application claims the priority benefit of Taiwan application Ser. No. 89100260, filed Jan. 10, 2000.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates in general to a method for forming a capacitor, and more particularly to a method for forming a capacitor of a mixed-mode device.
2. Description of the Related Art
Recently, applications for semiconductor devices have become wider and wider. For example, computers, communication produces, and consumer electronics produces comprise semiconductor devices, which have different functions. Semiconductor devices fabricated for different requirements are called application specific integrated circuits (ASIC).
Furthermore, with the progress in semiconductor process technologies, necessary capital expenditure is rapidly decreasing. Applications in electronic devices have been developed toward variety so that devices with a single function such as logic devices no longer satisfy requirements. Therefore, semiconductor processes are gradually developed toward integrating a logical device and a memory device on the same wafer, which structure is called a system on chip (SOC). A mixed-mode device comprising a capacitor and a complementary metal oxide semiconductor (CMOS) is one kind of ASIC.
FIG. 1
is a diagram showing a conventional capacitor structure of a mixed-mode device. Referring to
FIG. 1
, the conventional capacitor structure comprises a N-type conductive region
102
formed in a substrate
100
, a polysilicon layer
104
and a gate oxide layer
106
. N-type conductive region
102
is formed by doping N-type impurities into substrate
100
, polysilicon layer
104
, which is doped with an N-type dopant, serves as electrodes, and gate oxide layer
106
serves as a dielectric film. Conductive regions
102
a
are formed at two sides of the conductive region
102
in the substrate
100
. The conductive regions
102
a
are used to electrically connect to an external power source. The doped polysilicon layer
104
is simultaneously formed while forming a gate on the gate oxide layer
106
.
The conventional capacitor is a planar capacitor. The amount of charge stored in the conventional capacitor does not satisfy the high-capacitance requirement.
SUMMARY OF THE INVENTION
The invention provides a method for forming a capacitor of a mixed-mode device that satisfies the high-capacitance requirement. A substrate is provided. A pad oxide layer and a first mask layer are formed on the substrate. A first shallow trench and second shallow trenches are formed in the substrate by photolithography and etching processes. The first shallow trench is used to isolate active regions from each other. The second shallow trenches are used to form capacitors. A liner oxide layer is formed on an exposed surface of the substrate within the first shallow trench and the second shallow trenches. A dielectric layer is formed over the substrate and within the trenches. A portion of the dielectric layer on the first mask layer is etched to expose the first mask layer. The first mask layer and the pad oxide layer are removed. A second mask layer is provided over the substrate, by which the first shallow trench is covered and the second shallow trenches are exposed. The liner oxide layer and the dielectric layer within the second shallow trenches are removed. A first ion implantation process is performed to form a first conductive region in the substrate around the second shallow trenches. The second mask layer is removed. A gate oxide layer is formed on the substrate. A conductive layer is formed to fill in and over the second shallow trenches. A second ion implantation process is performed to form a second conductive region in the substrate around the conductive layer. The second conductive region electrically connects to the first conductive region. The second conductive region is also used to connect to an external power.
In the invention, the second shallow trenches, which are used to increase the surface area of a capacitor, and the first shallow trench, which is used for isolation, are simultaneously formed. The first conductive region in the substrate around the second shallow trenches is used as a lower electrode. The conductive layer over the gate oxide layer is used as an upper electrode. The gate oxide layer is used as a dielectric film between the lower and the upper electrodes. A trench-type capacitor is thus formed.
Fabrication of the trench-type capacitor can be integrated into a fabrication of CMOS so that the whole process is easily performed.
REFERENCES:
patent: 6093600 (2000-07-01), Chen et al.
patent: 6159874 (2000-12-01), Tews et al.
Bowers Charles
Brewster William M.
United Microelectronics Corp.
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