Metal working – Method of mechanical manufacture – Electrical device making
Reexamination Certificate
2002-02-19
2003-11-25
Arbes, Carl J. (Department: 3729)
Metal working
Method of mechanical manufacture
Electrical device making
C029S825000, C029S847000, C324S762010
Reexamination Certificate
active
06651325
ABSTRACT:
FIELD OF THE INVENTION
The present invention generally relates to a semiconductor fabrication method and system and more particularly, relates to a method for forming cantilever beam probe card and the probe card formed.
BACKGROUND OF THE INVENTION
As semiconductor integrated circuits continue to be dramatically reduced in size, the trend in electronic manufacturing has been toward increasingly smaller geometries particularly in integrated circuit technology in which a very large number of discrete circuit elements are fabricated on a single substrate or “wafer”. After fabrication, the wafer is divided into a number of rectangular-shaped chips or “dice” where each die presents a rectangular or other regular arrangement of metallized contact pads through which input/output connections are made. Although each die is eventually packaged separately, for efficiency sake, testing of the circuit formed on each die is preferably performed while the dies are still joined together on the wafer. One typical procedure is to support the wafer on a flat stage or “chuck” and to move the wafer in X, Y and Z directions relative to the head of the probing assembly so that the contacts on the probing assembly move from die to die for consecutive engagement with each die. Respective signal, power and ground lines are run to the probing assembly from the test instrumentation thus enabling each circuit to be sequentially connected to the test instrumentation.
One conventional type of probing assembly used for testing integrated circuits provides contacts that are configured as needle-like tips. These tips are mounted about a central opening formed in a probe card so as to radially converge inwardly and downwardly through the opening. When the wafer is raised beyond that point where the pads on the wafer first come into contact with these tips, the tips flex upwardly so as to skate forwardly across their respective pads thereby removing oxide buildup on the pads.
The problem with this type of probing assembly is that the needle-like tips, due to their narrow geometry, exhibit high inductance so that signal distortion is large in high frequency measurements made through these tips. Also, these tips can act in the manner of a planing tool as they wipe across their respective pads, thereby leading to excessive pad damage. This problem is magnified to the extent that the probe tips bend out of shape during use or otherwise fail to terminate in a common plane which causes the more forward ones of the tips to bear down too heavily on their respective pads.
Thus, in the course of testing semiconductor devices and circuits it becomes necessary to contact and electrically probe the devices and circuits to ascertain their function and determine failure mechanisms. To accomplish this, a finely pointed probe tip or group of finely pointed probe tips is brought into contact with the device or circuit by using pads connected to the device or circuit. As semiconductor devices become smaller and circuits denser, it becomes difficult to make electrical contact with the device with conventional probes, as the probe tips are either too large or too blunt to selectively contact only the intended device or circuit because they have a propensity to contact adjacent structures. Or, the tips are so thin as to bend when contact is attempted and slide off the probe terminal target circuit being tested. When multiple probes are required, it is often not possible to bring the correct number of probe tips close enough to each other because the size of the bodies will physically interfere with one another or will block the view of the target area being tested, thereby making alignment difficult or impossible.
As a result of these problems, pads on semiconductor devices which can number several hundred are often limited by the probe assemblies or probe rings used because of the size of the probe tips. This is especially true in the street or kerf regions between active dies on semiconductor wafers, wherein special test and process monitoring devices and circuits are often fabricated. The actual devices and monitoring structures are often very much smaller than the pads connected to them. A more compact probe assembly would allow smaller pads to be used allowing more devices in the same space or the same number of devices in a smaller space.
The present inventors thus recognize based on the foregoing, that a need exists for an acceptable micro tip that can be utilized with micro probes as semiconductor circuits continue to shrink. Users typically waste a great deal of time and effort attempting to fabricate an acceptable micro tip. To date, a reliable method for fabricating an acceptable micro tip has not been evidenced. The present inventors believe that implementing a micro tip in accordance with the invention described herein can thus solve these problems.
It is therefore an object of the present invention to provide an improved semiconductor manufacturing method and device thereof.
It is another object of the present invention to provide a method for forming a microtip of a microprobe on a probe card.
It is a further object of the present invention to provide a method for forming a microtip of a microprobe by utilizing micromachining manufacturing techniques.
It is another further object of the present invention to provide a method for fabricating a cantilever beam probe card by a micro-electro-mechanical system (MEMS) technology.
It is still another object of the present invention to provide a method for forming a probe card by using a sacrificial layer of oxide to release cantilever beams formed on the card.
It is yet another object of the present invention to provide a method for forming probe card by MEMS technology by forming cantilever beams from two different metals.
It is still another further object of the present invention to provide a method for forming a cantilever beam probe card that can be used for testing high pin count and fine pitch IC devices at low cost.
SUMMARY OF THE INVENTION
In accordance with the present invention, a method for forming a cantilever beam probe card and the probe card formed are disclosed.
In a preferred embodiment, a method for forming a cantilever beam probe card on a semiconducting substrate can be carried out by the operating steps of first providing a semiconducting substrate that has a top surface and a bottom surface; depositing an insulating material layer of at least 0.1 &mgr;m thickness on the top surface; patterning and etching at least two via holes in the insulating material layer; depositing a first metal layer of at least 0.15 &mgr;m thickness on top of and measured from the semiconducting substrate filling the at least two via holes and covering a top surface of the insulating material layer; depositing a second metal layer of at least 0.1 &mgr;m thickness on top of the first metal layer, the second metal layer being formed of a metal different than that used in forming the first metal layer; patterning and etching at least two via holes in the bottom surface of the semiconducting substrate exposing the at least two via holes formed in the insulating material layer; filling the at least two via holes in the semiconducting substrate with a metal forming at least two vias; patterning and etching at least two cone-shaped microprobes from the second metal layer; patterning and etching a trench in the first metal layer electrically insulating the at least two cone-shaped microprobes from each other; and etching away the insulating material layer from the top surface of the semiconducting substrate.
The method for forming a cantilever beam probe card on a semiconducting substrate may further include the step of bonding the at least two vias to a printed circuit board (PCB) or a ceramic substrate through solder bumps formed on the PCB or the ceramic substrate. The method may further include the step of etching away the insulating material layer by a wet etching process, or the step of patterning and etching the trench in the first metal layer by a dry etch or a wet etch process
Chen Yi-Shiau
Lee Cheng-Hong
Lee Hsin-Li
Arbes Carl J.
Industrial Technologies Research Institute
Tung & Associates
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