Method for forming an interconnection structure for conductive l

Details Method for forming an interconnection structure for conductive l Method for forming an interconnection structure for conductive l

1992-08-31

1993-11-16

Chaudhuri, Olik

Fishing, trapping, and vermin destroying

437190, 437193, 437195, H01L 2144, H01L 2148

Patent

active

052623521

ABSTRACT:
An interconnect structure is formed having a substrate (10). A conductive layer (14) is formed overlying the substrate (10). A conductive layer (18) is formed overlying the conductive layer (14). An opening (19) is etched through the conductive layer (18), exposing a top portion of conductive layer (14), and forming a sidewall of the conductive layer (18). An selective isotropic etch procedure is used to laterally recess the sidewall of the conductive layer (18). A sidewall spacer (22) is formed adjacent the sidewall of the conductive layer (18). A conductive layer (24) is formed within opening (19) and adjacent the spacer (22) to form an interconnection between conductive layers (24 and 14). The interconnection is self-aligned, and conductive layer (18) is reliably isolated from the interconnect due to the lateral recessed sidewall of the conductive layer (18).

REFERENCES:
patent: 4656732 (1987-04-01), Teng et al.
patent: 4700457 (1987-10-01), Matsukawa
patent: 4977105 (1990-12-01), Okamoto et al.
patent: 5045501 (1991-09-01), Grinberg
patent: 5051794 (1991-09-01), Mori
patent: 5091762 (1992-02-01), Watanabe
patent: 5100838 (1992-03-01), Dennison
patent: 5116776 (1992-05-01), Chan et al.
"A Split Wordline Cell for 16Mb SRAM Using Polysilicon Sidewall Contacts," by Itabashi et al., published via IEDM 1991, pp. 477-480.

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