Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Having substrate registration feature
Reexamination Certificate
1998-08-31
2003-03-18
Chaudhuri, Olik (Department: 2814)
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
Having substrate registration feature
C438S462000, C438S975000
Reexamination Certificate
active
06534378
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to integrated circuit manufacturing and, more particularly, to retaining a substantially transparent dielectric above alignment marks during polishing of the dielectric to ensure that the alignment marks are preserved for subsequent alignment thereto.
2. Description of the Related Art
Fabrication of an integrated circuit involves numerous processing steps. After gate areas have been defined on a semiconductor substrate and implant regions (e.g., source/drain regions) have been formed in the substrate, an interlevel dielectric is formed over the topography to make electrical contact to the gate areas and the implant regions. Interconnects are then formed across the interlevel dielectric to connect the implant regions and/or the gate areas through ohmic contacts formed earlier through the interlevel dielectric. Alternating levels of interlevel dielectric and interconnect may be placed across the semiconductor topography to form a multi-level integrated circuit.
A technique known as “photolithography” is generally used to pattern the various levels of an integrated circuit. Photolithography entails transferring an optical image to a photosensitive film from a patterned mask plate (i.e., reticle) placed in proximity to the film. The photosensitive film, i.e., “photoresist” is formed upon the layer of material to be patterned. A mask plate having both opaque and transparent regions is placed above the resist. Radiation is transmitted through only the transparent portions of the mask plate to the resist. The solubility of resist regions exposed to the radiation is altered by a photochemical reaction. A solvent may be used to remove the resist areas of higher solubility. The resulting patterned resist film serves to protect underlying conductive or dielectric material from etching or ion implantation.
It is critical to align successive layers of an integrated circuit to each other to ensure proper operation of the circuit. In particular, the mask plate pattern must be properly aligned to previously formed features in a semiconductor topography during the lithography process. In the extreme, lithographic misalignment may lead to shorting between structures that should be isolated from each other, and isolation of structures that should be coupled to each other. Typically, an alignment system, such as a stepper, is used to align the mask plate to the semiconductor topography. The alignment system may employ an alignment mark (e.g., a trench in the form of a geometric shape, such as a square, a “+”, or an “X”) which has been formed in the substrate as a reference point. Although the original alignment mark may be covered by subsequently deposited layers, the step height of the alignment mark (the depth of the trench) is replicated in those layers. The alignment system directs a laser beam to the replicated alignment mark residing in the most recently deposited layer. The light striking the replicated alignment mark is reflected back to sensing devices which detect the exact position of the alignment mark. Alignment is achieved by moving the mask plate until a feature, i.e., an alignment guide, in the mask plate is correctly positioned with respect to the alignment mark.
As successive layers are deposited across previously patterned layers of an integrated circuit, elevational disparities develop across the surface of each layer. If left unattended, the elevational disparities in each level of an integrated circuit can lead to various problems. For example, when an interconnect is placed across a dielectric layer having elevationally raised and recessed regions, step coverage problems may arise. Step coverage is defined as a measure of how well a film conforms over an underlying step and is expressed by the ratio of the minimum thickness of a film as it crosses a step to the nominal thickness of the film over horizontal regions. Furthermore, correctly patterning layers upon a topological surface containing fluctuations in elevation may be difficult using optical lithography. The depth-of-focus of the lithography alignment system may vary depending upon whether the resist resides in an elevational “hill” or “valley” area. The presence of such elevational disparities therefore makes it difficult to print high resolution features.
Techniques involving chemical and mechanical abrasion (e.g., chemical-mechanical polishing) to planarize or remove the surface irregularities have grown in popularity. As shown in
FIG. 1
, a typical chemical-mechanical polishing (“CMP”) process involves placing a semiconductor wafer
4
face-down on a polishing pad
6
which lies on or is attached to a rotatable table or platen
8
. A popular polishing pad medium comprises polyurethane or polyurethane-impregnated polyester felts. During the CMP process, polishing pad
6
and semiconductor wafer
4
may be rotated while a carrier
2
holding wafer
4
applies a downward force F upon polishing pad
6
. A “slurry” consisting of an abrasive and a fluid-based chemical is deposited from a conduit
9
positioned above pad
6
onto the surface of polishing pad
6
. The slurry may fill the space between pad
6
and the surface of wafer
4
. The polishing process may involve a chemical in the slurry reacting with the surface material being polished. The rotational movement of polishing pad
6
relative to wafer
4
causes abrasive particles entrained within the slurry to physically strip the reacted surface material from wafer
4
. The pad
6
itself may also physically remove some material from the surface of the wafer
4
. The abrasive slurry particles are typically composed of silica, alumina, or ceria.
Unfortunately, planarizing the layers of an integrated circuit may also planarize the alignment mark areas which have been transferred to those layers from the substrate. Absent the topography of the alignment marks, the lithography alignment system may be incapable of properly aligning a mask plate to the previously patterned layers. The commonly used solution to dealing with planarized alignment marks uses a photolithographic step to expose the alignment mark areas and protect the rest of the substrate with resist. In the next step, the planarized dielectric in the alignment mark areas is etched away so as to recover the original pattern of the alignment marks. This solution therefore adds two steps to the process flow. It would therefore be desirable to develop methods for preserving alignment marks in a substrate and precisely aligning a mask plate to a planarized semiconductor topography having such marks. That is, an alignment technique is desired which does not require the replication of alignment marks from the substrate into subsequent layers to properly align those layers.
SUMMARY OF THE INVENTION
The problems outlined above are in large part solved by an embodiment of the present invention in which a substantially transparent dielectric is retained above one or more alignment marks while polishing the dielectric. The optical property of the alignment mark is preserved even though the polishing process removes its replicated pattern from the overlying dielectric. The alignment mark may be formed by etching an alignment mark trench into a semiconductor substrate. The semiconductor substrate may comprise a bulk semiconducting material, such as Si, SiGe, Ge, GaAs, SiGeAs, etc., which may be conventionally doped with N-dopants, such as P, As, Sb, S, Se, and/or P-dopants, such as B, BF
2
, upon which subsequent thin films are deposited and/or patterned. A silicon nitride (“nitride”) layer may be deposited on the substrate-embodied alignment mark during a shallow trench isolation process, before or after forming the shallow trench. The nitride layer may form a mask during the formation of densely packed isolation trenches within the substrate. Advantageously, because of its translucence, the nitride layer may be retained above the alignment mark (in the alignment mark trench) while a transparent dielectric is deposited across the topog
Kallingal Chidambaram G.
Madhavan Sriram
Ramkumar Krishnaswamy
Chaudhuri Olik
Conley & Rose & Tayon P.C.
Cypress Semiconductor Corp.
Daffer Kevin L.
Mai Anh D.
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