Method for forming an integrated circuit container having partia

Details Method for forming an integrated circuit container having partia Method for forming an integrated circuit container having partia

1998-02-19

1999-07-27

Nguyen, Tuan H.

Semiconductor device manufacturing: process

Making passive device

Stacked capacitor

438255, H01L 2120

Patent

active

059306416

ABSTRACT:
Disclosed is a bi-level container capacitor in which a bottom portion is smooth and an upper portion is rugged or rough. Once the container has been formed within a thick insulating layer, a conductive layer is conformally deposited over the container interior surfaces. The bottom portion of the container, which is narrowly confined between two gate electrodes, is isolated from further processing by filling the bottom portion with a protective film. A rugged conductive layer is then formed only on the surface of the upper portion of the container, after which the protective film is removed from the bottom portion. As a result, a capacitor bottom plate conforms to the interior surfaces of the container, the bottom plate including a rugged upper portion and a smooth bottom portion.

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