Method for forming an insulator between layers of conductive mat

Metal treatment – Process of modifying or maintaining internal physical... – Chemical-heat removing or burning of metal

Patent

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

29571, 29578, 29580, 148174, 156643, 156657, 156662, 204192E, 357 24, 357 59, H01L 2122, H01L 21306

Patent

active

042343623

ABSTRACT:
A method for forming an insulator between conductive layers, such as highly doped polycrystalline silicon, that involves first forming a conductive layer of, for example, polycrystalline silicon on a silicon body having substantially horizontal and substantially vertical surfaces. A conformal insulator layer is formed on the substantially horizontal and substantially horizontal and vertical surfaces. Reactive ion etching removes the insulator from the horizontal layer and provides a narrow dimensioned insulator on the vertical surfaces silicon body. Another conductive layer, which may be polycrystalline silicon, is formed over the insulator. The vertical layer dimension is adjusted depending upon the original thickness of the conformal insulator layer applied.

REFERENCES:
patent: 3750268 (1973-08-01), Wang
patent: 3943543 (1976-03-01), Caywood
patent: 3966577 (1976-06-01), Hochberg
patent: 3984822 (1976-10-01), Simko et al.
patent: 3996657 (1976-12-01), Simko et al.
patent: 3996658 (1976-12-01), Takei et al.
patent: 4031608 (1977-06-01), Togei et al.
patent: 4072545 (1978-02-01), De La Moneda
patent: 4074300 (1978-02-01), Sakei et al.
patent: 4080719 (1978-03-01), Wilting
patent: 4097885 (1978-06-01), Walsh
patent: 4104090 (1978-08-01), Pogge
patent: 4157269 (1979-06-01), Ning et al.
patent: 4174251 (1979-11-01), Paschke
Gdula et al., "CCD . . . Polysilicon", IBM Technical Disclosure Bulletin, vol. 21, No. 5, (10/78), pp. 1865-1866.
Chang et al., "Transistor . . . Metal", IBM Technical Disclosure Bulletin, vol. 21, No. 2 (7/78), pp. 578-579.
Deines et al., "Process . . . Geometries", IBM Technical _Disclosure Bulletin, vol. 21, No. 9 (2/79), pp. 3628-3629.
Abbas et al., "Extending . . . Processing ", IBM Technical Disclosure Bulletin, vol. 20, No. 4 (9/77), pp. 1376-1378.
Pogge, "Narrowline . . . Method", IBM Technical Disclosure Bulletin, vol. 6 (11/76), p. 2354.
Bersin, "A Survey . . . Processes", Solid State Technology (5/76), pp. 31-36.
Critchlow, "High Speed . . . Lithography", vol. 9, No. 2 (2/76), pp. 31-37.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Method for forming an insulator between layers of conductive mat does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method for forming an insulator between layers of conductive mat, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for forming an insulator between layers of conductive mat will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-596411

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.