Method for forming a wiring layer

Details Method for forming a wiring layer Method for forming a wiring layer

1993-02-22

1995-05-30

Hearn, Brian E.

Fishing, trapping, and vermin destroying

437233, 437241, 437187, 437982, H01L 21265, H01L 21465

Patent

active

054200776

ABSTRACT:
A method for a wiring layer on a semiconductor substrate wherein a contact hole for a wiring layer is formed by laminating a lower insulating layer and an etching barrier layer on the semiconductor substrate providing electrodes via a gate insulating film, forming a hole in the etching barrier layer using a first mask pattern having a hole pattern in which a diameter of the hole thereof is larger than that of the contact hole to be formed, laminating an upper insulating layer and a second mask pattern having a hole pattern in which a diameter of the hole thereof is substantially the same as that of the contact hole, subjecting the lower and upper insulating layers and the gate insulating film to an isotropic etching and an anisotropic etching, utilizing the second mask pattern, thereby forming a contact hole having no exposure of the etching barrier layer at the side of wall of the contact hole.

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Wolf et al. "Silicon Processing for the VLSI ERA" vol. 1, pp. 520, 1986, pp. 559-561.
Wolf et al; "Silicon Processing for the VLSI"; vol. 1; 1986; pp. 175-177, 531-534, 581.

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