Method for forming a void free isolation pattern and resulting s

Details Method for forming a void free isolation pattern and resulting s Method for forming a void free isolation pattern and resulting s

1986-05-23

1987-08-25

James, Andrew J.

Fishing, trapping, and vermin destroying

357 50, 437 62, H01L 2712

Patent

active

046896562

ABSTRACT:
The void-free pattern of isolation in a semiconductor substrate is described. There is contained within a semiconductor body a pattern of substantially vertically sided trenches. The pattern of isolation trenches isolate regions of monocrystalline semiconductor material which may contain active and passive semiconductor devices. The depth of the pattern of trenches is greater than about 3 micrometers. A first insulating layer is located upon the sidewalls of the trenches. The base or bottom of the trenches is open to the monocrystalline semiconductor body. An epitaxial layer extending from the base of the trenches fills the pattern of trenches up to between about 500 to 1500 nanometers from the upper surface of the trenches. A capping second insulating layer fills the additional portion of the pattern of trenches above the upper surfaces of the epitaxial layer for isolation of the pattern of trenches from the ambient. It is the dense epitaxial monocrystalline semiconductor which prevents the formation of voids within the pattern of trenches. The epitaxial layer must be grown in such a way so as no spurious growth occurs upon the principal surfaces of the substrate, because such growth would prevent the satisfactory chemical-mechanical polishing of the C.V.D. insulator layer.

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