Semiconductor device manufacturing: process – Chemical etching – Liquid phase etching
Reissue Patent
1999-04-16
2004-01-13
Nguyen, Tuan H. (Department: 2813)
Semiconductor device manufacturing: process
Chemical etching
Liquid phase etching
C438S628000, C438S629000, C438S644000, C438S675000, C257S774000, C257S763000
Reissue Patent
active
RE038383
ABSTRACT:
FIELD OF THE INVENTION
The invention relates to a method of forming a via plug in a semiconductor device, more particularly, it relates to a method of forming a via plug by forming metal nuclei on the surface of a metal layer underlying a via hall and then etching the metal layer exposed between the metal nuclei by the wet etching method so that a plurality of etching grooves are formed thereupon. The formation of such grooves has the effect of increasing the bottom surface area of the via hall, thereby increasing the adhesive strength to a contact surface of the via hall and decreasing the via resistance.
INFORMATION DISCLOSURE STATEMENT
Generally, as integration of a semiconductor device is increased, the size of the via hall diminishes while the aspect ratio increases. If the depth of the via halls are different from each other, the via plug is formed on the via halls using tungsten. In order to form a uniform and complete via plug, pretreatment of the via halls is important. If the surface of the via halls is not uniform prior to and during application of the wet etching process, particles, such as a native oxide layer and polymer, are generated on the surface of the metal layer underlying the via halls. Accordingly, when the via plug is formed on the via halls, the tungsten is deposited with a lack of uniformity resulting in increased via resistance to; such increased resistance has a deleterious effect on subsequent processes culminating in the lowering of the electrical connecting characteristic of the semiconductor device.
Therefore, it is an object of the invention to provide a method of forming a via plug in a semiconductor device by which a fluorine particle and a native oxide layer formed on the surface of the metal layer underlying a via hole are removed and metal nuclei are formed on the surface of the metal layer. The metal layer between the metal nuclei is then exposed and etched by the wet etching method so as to increase the surface area of the adhesive contact area, thereby decreasing the via resistance while increasing the adhesive strength.
SUMMARY OF THE INVENTION
A method of forming a via plug according to the present invention in order to achieve the above object is comprised of the following steps:
A first metal layer is formed on a substrate and first, second and third insulating layers are sequentially deposited on the resulting substrate; the third insulating layer is then planarized;
A desired portion of the third, second and first insulating layer are etched using a contact mask until the first metal layer is exposed, thereby forming a via hole;
The via hole is pretreated by the dry etching method and then metal is selectively deposited on the surface of the first metal layer underlying the via hole using a metal depositing reactor, thereby forming metal nuclei;
The first metal layer exposed between the metal nuclei is etched so that a plurality of etching grooves is formed on the first metal layer.
REFERENCES:
patent: 5198389 (1993-03-01), van der Putten et al.
patent: 5232872 (1993-08-01), Ohba
patent: 5270256 (1993-12-01), Bost et al.
patent: 5320979 (1994-06-01), Hashimoto et al.
patent: 5394012 (1995-02-01), Kimura
patent: RE36475 (1999-12-01), Choi
patent: 0168828 (1986-01-01), None
patent: 0216017 (1987-04-01), None
patent: 0255911 (1988-02-01), None
patent: 0300414 (1989-01-01), None
patent: 0168828 (1992-01-01), None
patent: 0500456 (1992-08-01), None
patent: 2135123 (1984-08-01), None
patent: 2253938 (1992-09-01), None
patent: 0064927 (1982-04-01), None
patent: 0061323 (1987-03-01), None
patent: 62061323 (1987-03-01), None
patent: 0156820 (1987-07-01), None
patent: 4056237 (1992-02-01), None
patent: 04-196343 (1992-07-01), None
patent: 4216548 (1992-08-01), None
patent: 5259110 (1993-10-01), None
Patent Abstracts of Japan, vol. 011, No. 249, Aug. 13, 1987.
Panabiere et al., “Concept and Processing of Buring Photomasks,” Revue de Physique Applique, vol. 25, No. 8, pp. 859-865, Aug. 1, 1990.
Chen, F.S., et al., “Advanced Triple Level Metal Interconnection for 0.6&mgr;m/5 V High Density/High Performance ASIC Technolgy,”VMIC Conference(Jun. 8-9, 1993).
Hyundai Electronics Industries Co,. Ltd.
Nguyen Tuan H.
Townsend and Townsend / and Crew LLP
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