Method for forming a vertical transistor with a stacked capacito

Details Method for forming a vertical transistor with a stacked capacito Method for forming a vertical transistor with a stacked capacito

1994-03-11

1995-07-04

Chaudhuri, Olik

Fishing, trapping, and vermin destroying

437 60, 437919, H01L 2170, H01L 2700

Patent

active

054299772

ABSTRACT:
There is shown a method for fabricating a vertical DRAM cell which includes a field effect transistor having a gate electrode and source/drain elements and a capacitor. There is provided a pattern of field oxide isolation in a silicon substrate wherein there are a pattern of openings to the silicon substrate. A pattern is formed of bit lines and a pattern of lines of holes with a hole located within each of the openings to said silicon substrate which lines of holes and bit lines are perpendicular to one another and which the lines cross at the planned locations of the vertical DRAM cell at the pattern of openings to the silicon substrate. A gate dielectric is formed on the surfaces of the holes. A doped polysilicon layer is formed in and over the holes so that it covers the gate dielectric and the field oxide isolation. A silicon nitride layer is formed over the doped polysilicon layer. Patterning and etching is done to the silicon nitride layer and doped polysilicon layer to form the opening for the capacitor node contact to the buried source/drain of the vertical field effect transistor (switching device for the storage signal) and establish said gate electrode in the hole and word line pattern over the field oxide insulator. A silicon oxide spacer is formed over the sidewalls of the silicon nitride and doped polysilicon layer. A capacitor is formed in and over the hole to complete the vertical DRAM cell.

REFERENCES:
patent: 4845539 (1989-07-01), Inoue
patent: 4891327 (1990-01-01), Okumura
"Advanced Cell Structure for Dynamic RAMs" by Nicky C. C. Lu, Pub in IEEE Circuits and Device Magazine, Jan. 1989 pp. 27-36.
W. F. Richardson et al., "A Trend Transistor Cross-Pointe DRAM Cell", Pub. in 1985 DRAM 85 pp. 714-717.

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