Method for forming a two-layered polysilicon gate electrode in a

Details Method for forming a two-layered polysilicon gate electrode in a Method for forming a two-layered polysilicon gate electrode in a

1994-11-15

1995-08-15

Hearn, Brian E.

Fishing, trapping, and vermin destroying

437189, 437191, 437193, H01L 21265

Patent

active

054419042

ABSTRACT:
A method is disclosed for forming a gate electrode having two polysilicon layers and a tungsten silicide layer to prevent fluorine gas diffusion along grain boundaries from penetrating into a gate oxide film.
This method for forming a gate electrode is comprised of sequentially forming a gate oxide film and a first polysilicon layer on a silicon substrate, enlarging the grain size of the first polysilicon layer by heat treatment, introducing a reagent gas, either SiH.sub.4 or Si.sub.2 H.sub.6, to further adjust the grain size within said layer, forming a second polysilicon layer on the first polysilicon layer, enlarging the grain size of the second polysilicon layer by heat treatment, introducing a reagent gas, either Si.sub.2 H.sub.6 or SiH.sub.4, whichever one was not used to treat the first polysilicon layer, forming a tungsten silicide layer on the second polysilicon layer, and patterning the tungsten silicide layer, the second polysilicon layer and the first polysilicon layer by means of a mask etching process.

REFERENCES:
patent: 4354309 (1982-10-01), Gardiner et al.
patent: 4816425 (1989-03-01), McPherson
patent: 4829024 (1989-05-01), Klein et al.
patent: 4868140 (1989-09-01), Yonehara
patent: 5093700 (1992-03-01), Sakata
patent: 5212105 (1993-05-01), Kizu et al.
patent: 5350698 (1994-09-01), Huang et al.

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