Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Grooved and refilled with deposited dielectric material
Reexamination Certificate
2001-05-21
2002-04-16
Bowers, Charles (Department: 2813)
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
Grooved and refilled with deposited dielectric material
C438S424000, C438S426000, C438S435000, C257S510000
Reexamination Certificate
active
06372604
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method for forming a trench type element isolation structure to be used for a semiconductor integrated circuit and trench type element isolation structure.
2. Description of the Prior Art
In a semiconductor integrated circuit, in order to eliminate electric interference between the elements in operation and control each element in fully independent state, elements are isolated from one another. Especially, a trench type element isolation trench is a structure filled with an insulator, and, as a bird's beak does not occur, it is an indispensable element isolation structure for making the semiconductor integrated circuit into miniature size.
FIGS. 13A-13F
are sectional views of a method of forming a conventional trench type element isolation structure. First, as shown in
FIG. 13A
, an under-layer oxide film (first thermal oxidation film)
2
and a silicon nitride film
3
are sequentially deposited on a silicon substrate
1
, after which, with a photolithographic pattern (not illustrated) used as a mask, silicon nitride film
3
and under-layer oxide film
2
are sequentially patterned to form a groove in silicon substrate
1
.
Next, as shown in
FIG. 13B
, a thermal oxidation film
10
is formed on an inner wall of the groove by thermal oxidation, after which an imbedding oxide film
11
is laid over the whole surface by CVD step.
Next, as shown in
FIG. 13C
, the imbedded oxide film
11
formed on the upper part of the nitride film
3
by a CMP step using a silicon nitride film
3
as a stopper is eliminated to allow the imbedded oxide film
11
to remain only in the groove.
Next, as shown in
FIG. 13D
, the silicon nitride film
3
is eliminated by heated phosphoric acid, after which the CVD oxide film
20
is accumulated on the whole surface by CVD step.
Next, as shown in
FIG. 13E
, a CVD oxide film
20
′ is allowed to remain only on the side wall of the imbedded oxide film
11
by carrying out anisotropic etching.
Finally, as shown in
FIG. 13F
, by eliminating the under-layer oxide film
2
with hydrofluoric acid, a trench type element isolation structure is completed.
In a method of forming a trench type element isolation structure, it is essential to remove ultimately the under-laid oxide film
2
formed on the activated region
23
. However, in the conventional structure trench type element isolation structure, the CVD oxide film
20
′ is formed by CVD and the etching speed in hydrofluoric acid is larger than that of the thermal oxidation film therefore in removing under-laid oxide film
2
shown in
FIG. 13F
, the CVD oxide film
20
′ is also etched and, hence, fails perform the function as protective film for the oxide film
11
imbedded in the groove. Thus the imbedded oxide film
11
in the groove is also etched in the edge part, resulting in formation of a recess
21
on the edge part of the imbedded oxide film in the groove.
In an integrated circuit, as shown in
FIG. 16
, there may be a case where a gate electrode
22
is formed on said trench type element isolation to take a structure to control the transistor formed on the activated region
23
by said gate electrode
22
. In such a case, due to the existence of the recess
21
, the gate electrode
22
does not become smooth shape on the edge part of the trench but concentration of an electric field occurs, which may be a cause for the reverse narrow channel effect to show lowering of the threshold value of the transistor. Especially, as the integration of the semiconductor elements progresses and the width of the activated region
23
(gap between the adjacent trenches) becomes narrower, the effect of the reverse narrow channel effect becomes remarkable, thereby making it extremely difficult to control the threshold voltage of the transistor to give ill effect on the circuit operation.
Accordingly, the present invention has its object to provide a method for forming a trench type element isolation structure which is free from formation of recess in an edge part of a trench type element isolation imbedded oxide film.
SUMMARY OF THE INVENTION
In view of the above, the present inventors made strenuous study, and as a result found out that, by forming a thermal oxidation film having higher etching resistance than the CVD film not only on the surrounding of the imbedded oxide film inside the groove formed on the silicon substrate but also on the lateral side of the imbedded oxide film projecting upward from the silicon substrate, formation of recess on the edge part of the imbedded oxide film in the step of removing the first thermal oxidation film can be prevented, and the reverse narrow channel effect of the transistor wherein a gate electrode is formed on a trench type element isolation structure can be suppressed, and completed the present invention.
According to the present invention, there is provided a method for forming a trench type element isolation structure wherein an imbedded oxide film projecting upward from the silicon substrate surface is imbedded in a groove formed on a silicon substrate through a thermal oxidation film, comprising; a) a step of forming a non-single crystal silicon film on said silicon substrate through a first thermal oxidation film, b) a step of forming a groove extending from the surface of said non-single crystal silicon film to the inside of said silicon substrate, c) a thermal oxidation step for forming second and third thermal oxidation films on the inside surface of said groove including said groove wall and said lateral side wall of said non-single crystal silicon film, and d) a removing step for removing said non-single crystal silicon film excluding said third thermal oxidation film to have said third thermal oxidation film formed on the lateral side projecting upward from the surface of said silicon substrate of said imbedded oxide film.
According to such a method, because the surroundings of the imbedded oxide film, not only the silicon substrate surface inside the groove but also the lateral side of the upward projecting part from the silicon substrate surface, are surrounded by the thermal oxidation film having the higher etching resistance than the CVD oxide film, such thermal oxidation film is less liable to be etched in the etching step of the first thermal oxidation film.
That is to say, in the conventional method, the CVD oxide film formed on the surroundings of the imbedded oxide film projecting upward from the silicon substrate surface showed formation of recess at the edge part of the imbedded oxide film inside the groove, by being simultaneously etched in the etching step of the first thermal oxidation film. To the contrary, according to the present invention method, on the lateral side of the imbedded oxide film projecting upward from the silicon substrate surface is provided with a thermal oxidation film having higher etching resistance than the CVD oxide film, so that the film is less liable to be etched in the etching step of said first thermal oxidation film, the lateral side of the imbedded oxide film is protected, and it becomes possible to prevent formation of recess in the edge part of the imbedded oxide film.
Thus, in the transistor having a gate electrode formed on a trench type element isolation structure, because of no formation of recess on the imbedded oxide film inside the isolation groove, concentration of electric fields in the gate electrode formed on the imbedded oxide film as in the conventional instance can be prevented, and it becomes possible to suppress the reverse narrow channel effect of transistor.
The present invention also provides a method for forming a trench type element isolation structure which comprises, further between said thermal oxidation step and said removing step, a deposition step for depositing said imbedded oxide film inside said groove and on said non-single crystal silicon film, and a film-thinning step for reducing the film thickness from the upper surface of the imbedded oxide film until the non
Horita Katsuyuki
Kuroi Takashi
Sakai Maiko
Blum David S
Bowers Charles
McDermott & Will & Emery
Mitsubishi Denki & Kabushiki Kaisha
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