Method for forming a trench structure in a silicon substrate

Details Method for forming a trench structure in a silicon substrate Method for forming a trench structure in a silicon substrate

2000-03-24

2002-01-08

Lebentritt, Michael S. (Department: 2824)

Semiconductor device manufacturing: process

Formation of electrically isolated lateral semiconductive...

Grooved and refilled with deposited dielectric material

C438S427000, C438S723000, C438S789000, C438S969000

Reexamination Certificate

active

06337255

ABSTRACT:

BACKGROUND OF THE INVENTION
Field of the Invention
The invention relates to a method for forming a trench structure in a silicon substrate. The trench structure electrically insulates a first region of the substrate from a second region of the substrate.
As a result of the rising integration level in semiconductor components, the requirements made of the electrical insulation of adjacent active regions on a semiconductor substrate are continuously becoming more and more stringent. In the case of the local oxidation of silicon (LOCOS) technique currently used to fabricate integrated circuits on a large scale, the electrical insulation of adjacent MOS transistors is achieved by the localized formation of a field oxide. In this method, a so-called bird's beak is formed in the transition region between the field oxide and the gate oxide. The bird's beak has the disadvantage that, on account of its lateral extent, it reduces the semiconductor substrate area t is available for active regions, and thus leads to significant difficulties in the case of structures in the region of 0.35 &mgr;m or less.
The trench isolation technique including shallow trench isolation (STI) has been proposed as an alternative to the LOCUS technique. In the case of the trench isolation technique, narrow trenches are etched into the monocrystalline silicon substrate and subsequently filled with an insulating material. The filled trenches then act as space-saving electrical insulation barriers between active regions. This technique is highly suitable for the electrical insulation both of closely adjacent bipolar transistors and of p-channel and n-channel MOS transistors in CMOS circuits. What is disadvantageous, however, is that the use of this technique necessitates a high process complexity and is therefore associated with high costs.
The high process complexity can essentially be attributed to the fact that after the trench has been filled with silicon dioxide, the trench profile is transferred to the silicon dioxide layer and, therefore, a further, leveling layer, for example a photoresist or a polysilicon layer, has to be applied to the silicon dioxide layer, which gives rise to evenness problems on account of the different layer materials in the course of the subsequent planar removal of the layer. These then have to be compensated for by additional processes in order to obtain a planar substrate surface again after the removal of the silicon dioxide layer.
SUMMARY OF THE INVENTION
It is accordingly an object of the invention to provide a method for forming a trench structure in a silicon substrate which overcomes the above-mentioned disadvantages of the prior art methods of this general type, which enables a trench structure to be fabricated in a silicon substrate in the simplest and most cost-effective manner possible.
With the foregoing and other objects in view there is provided, in accordance with the invention, a method for forming a trench structure in a silicon substrate, the trench structure electrically insulating a first region of the silicon substrate from a second region of the silicon substrate, the method which includes:
growing a thermal oxide layer on a surface of the silicon substrate;
applying and patterning a mask layer over the thermal oxide layer resulting in a patterned mask layer;
etching a trench using the patterned mask layer down to a predetermined depth into the silicon substrate;
depositing a substantially conformal covering oxide layer with substantially uniform thickness that is sufficient for completely filling the trench;
depositing a polysilicon layer on the conformal covering oxide layer, a thickness of the polysilicon layer corresponding at least the predetermined depth of the trench;
chemical mechanical polishing of the polysilicon layer as far as a level of a surface of the conformal covering oxide layer with high selectivity between a polysilicon material of the polysilicon layer and an oxide material of the conformal covering oxide layer; and
substantially nonselective, joint etching of the polysilicon material of the polysilicon layer and of the oxide material of the covering oxide layer while maintaining a planar surface produced in accordance with the chemical mechanical polishing step, the substantially nonselective etching step being carried out at least until all the polysilicon material of the polysilicon layer being removed in a region of the trench.
The effect achieved by the nonselectivity of the etching step is that the evenness produced in the preceding chemical mechanical polishing step (CMP: Chemical Mechanical Polishing) is preserved during the joint etching of the polysilicon material and the oxide material, until all the polysilicon material has been removed. This enables the joint removal of the polysilicon material and the oxide material by a single, cost-effective etching step. As a rule, a further polishing step is no longer required. Furthermore, the procedure also permits the setting of a defined oxide residual layer thickness over the silicon, provided that the thickness of the covering oxide layer deposited beforehand was larger than the depth of the trench by more than the desired residual layer thickness.
The nonselective etching step is preferably a plasma etching step, NF
3
/N
2
/CHF
3
gases preferably being used as etching gases.
In an advantageous manner, a selective etching step for removing the oxide material can be carried out after the nonselective etching step. This permits a predetermined distance between the surface of the silicon substrate and the surface of the trench oxide to be set by the etching of the oxide deposited in the trench. In addition, the selective etching step can be used for removing oxide material outside the trench.
In principle, the method according to the invention does not require the application of the silicon nitride layer to the thermal oxide layer, since the stopping effect of the silicon nitride layer which is utilized in a CMP step in the prior art is not required in this case. However, it may continue to be expedient for other reasons to provide the silicon nitride layer, for example in order to use it as a mask layer for the trench etching.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in a method for forming a trench structure in a silicon substrate, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.


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Wolf, Stanley “Silicon Processing for the VLSI Era vol. 1: Process Technology”, Lattice Press, 1986, pp. 175-182, 191-195.*
“Method for planarizing over shallow trenches filled with silicon dioxide”, dated Feb. 1990, IBM Technical Disclosure Bulletin, vol. 32, No. 9A, pp. 439 and 440.

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