Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Grooved and refilled with deposited dielectric material
Patent
1995-04-04
1998-07-28
Fourson, George R.
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
Grooved and refilled with deposited dielectric material
438437, H01L 2176
Patent
active
057862630
ABSTRACT:
The reliability of integrated circuits fabricated with trench isolation is improved by forming a trench isolation structure with a void-free trench plug (36). In one embodiment, a polysilicon layer (28) is formed within a trench (22) and then subsequently oxidized to form a first dielectric layer (30). The first dielectric layer (30) is then etched and a second dielectric layer (34) is subsequently formed over the etched dielectric layer (32). A portion of the second dielectric layer (34) is then removed using chemical-mechanical polishing to form a void-free trench plug (36) within the trench (22). In addition, reliability is also improved by minimizing subsequent etching of trench plug (36) after it has been formed.
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Cooper Kent J.
Fourson George R.
Motorola Inc.
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