Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Grooved and refilled with deposited dielectric material
Reexamination Certificate
1999-07-20
2003-02-25
Fourson, George (Department: 2823)
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
Grooved and refilled with deposited dielectric material
C438S762000
Reexamination Certificate
active
06524931
ABSTRACT:
FIELD OF THE INVENTION
This invention relates generally to semiconductor devices, and more specifically to a method for forming a trench isolation structure in an integrated circuit.
BACKGROUND OF THE INVENTION
The semiconductor industry continually strives to increase device performance and device density by reducing device dimensions. For a given chip size, device density can be increased by reducing the lateral distance separating active devices, or the device isolation width. The desire to reduce device isolation width, while maintaining the necessary electrical isolation between adjacent active devices, has led to the development of several different isolation schemes.
One technique which as been proposed for device isolation in high density integrated circuits is trench isolation. With trench isolation, field oxide encroachment of the surrounding active regions is eliminated, and therefore device isolation width can be reduced. Unfortunately, integrated circuits fabricated with existing trench isolation schemes often suffer from high leakage currents, and thus have poor reliability. One reason for this high leakage current is the formation of parasitic transistors along the trench sidewall. With existing trench isolation schemes the trench fill is often recessed into the trench such that a significant portion of the trench sidewall is no longer covered by the trench fill. As a result, when a transistor gate electrode is subsequently formed over an active region, which is abutting the trench sidewall, a portion of the gate electrode extends along the uncovered portion of the trench sidewall. This forms a parasitic transistor, which is in series with the conventional transistor formed along the horizontal surface of the active region. Because this parasitic transistor is formed along the trench sidewall it has a threshold voltage that is lower than that of the conventional horizontal transistor. Therefore, at voltages where the horizontal transistor is designed to be turned off the parasitic transistor continues to conduct a leakage current. In addition, the reliability of integrated circuits fabricated with existing trench isolation schemes are also adversely affected by isolation trenches that have voids or keyholes formed within them. If these voids or keyholes become exposed during the trench planarization process, then adjacent gate electrodes can be shorted to one another by conductive filaments subsequently formed within the void or keyhole. Moreover, void formation becomes more problematic as trench widths decrease and the aspect ratio of the trenches increases in order to meet high density integrated circuit requirements. Accordingly, a need exists for a trench isolation structure that allows high density integrated circuits to be fabricated with improved reliability.
REFERENCES:
patent: 4523369 (1985-06-01), Nagakubo
patent: 4666556 (1987-05-01), Fulton et al.
patent: 4714520 (1987-12-01), Gwozdz
patent: 4927780 (1990-05-01), Roth et al.
patent: 5112772 (1992-05-01), Wilson et al.
patent: 5175123 (1992-12-01), Vasquez et al.
patent: 5246537 (1993-09-01), Cooper et al.
patent: 5294562 (1994-03-01), Lur et al.
patent: 5316965 (1994-05-01), Philipossian et al.
patent: 5387540 (1995-02-01), Poon et al.
patent: 5786263 (1998-07-01), Perera
patent: 5817566 (1998-10-01), Jang et al.
patent: 5904540 (1999-05-01), Sheng et al.
patent: 5904542 (1999-05-01), Gilmer et al.
patent: 6037018 (2000-03-01), Jang et al.
patent: 6265281 (2001-07-01), Reinberg
patent: 6350662 (2002-02-01), Thei et al.
patent: 0 296 754 (1988-12-01), None
patent: 1-246860 (1989-02-01), None
patent: 01246860 (1989-10-01), None
patent: 436981 (2001-05-01), None
patent: 436981 (2001-05-01), None
IBM Corpo., 1979, “Method for Forming Shallow Junction Semiconductor Devices”, pp. 4868-4870.
T.A. Shankoff et al., “Bird's Beak Configuration & Elimination of Gate Oxide Thinning Produced during Selective Oxidation”, J. Electrochem. Soc.:Solid-State Science and Tech., Jan. 1980, pp. 216-222.
C.A.Goodwin et al., “MOS Gate Oxide Defects Related to Treatment of Silicon Nitride Coated Wafers Prior to Local Oxidation”, J. Electrochem. Soc.: Solid-State Sci. & Tech., May 1982, pp. 1066-1070.
G. Fuse et al., “A Practical Trench Isolation Technology with a Novel Planarization Process”, Semiconductor Research Center, Matsushita Elec. Ind.Co., 732-IEDM 1987 IEEE, pp. 732-735.
Fourson George
Meyer George R.
Motorola Inc.
Vo Kim-Marie
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