Method for forming a transistor comprising layers of silicon dio

Details Method for forming a transistor comprising layers of silicon dio Method for forming a transistor comprising layers of silicon dio

1972-10-13

1977-11-22

Tupman, W.

Metal working

Method of mechanical manufacture

Assembling or joining

29578, B01J 1700

Patent

active

040588874

ABSTRACT:
A method of manufacturing an insulated gate field effect transistor comprising providing a semiconductor body portion of one type conductivity, providing on a surface of said body portion an impurity masking layer having two adjacent apertures with the portion of the masking layer between said apertures and part of its thickness being of a masking material other than silicon dioxide and also capable of masking the silicon against oxidation, providing by impurity introduction through said apertures spaced surface regions of opposite type conductivity in said body portion, subjecting at least the surface portions of the body portion overlying the opposite type surface regions and adjacent the oxidation masking material to an oxidation treatment causing thereon the growth of a silicon dioxide that penetrates into the body portion except where masked by the oxidation masking material forming a silicon mesa under said oxidation masking material, applying a gate electrode insulated from and over the surface portion extending between the opposite type surface regions, and applying source and drain connections to the opposite type surface regions.

REFERENCES:
patent: 3290613 (1966-12-01), Theriault
patent: 3422321 (1969-01-01), Tombs
patent: 3438873 (1969-04-01), Schmidt

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