Fishing – trapping – and vermin destroying
Patent
1991-10-29
1992-12-15
Chaudhuri, Olik
Fishing, trapping, and vermin destroying
437 56, 437 28, 437 33, 437979, 148DIG9, H01L 2172
Patent
active
051717026
ABSTRACT:
A BiCMOS structure and a method for making the same is disclosed, where the dielectric layer between the emitter electrode and the base region is formed of a deposited dielectric. After definition of the bipolar and MOS moat regions, a layer of polysilicon is deposited thereover, and removed from the bipolar region. The base implant is performed either prior to or after the etch of the polysilicon layer. A layer of TEOS oxide is formed thereover and is etched to remain in portions of the bipolar region, with an emitter contact formed therethrough and a portion of the bipolar region exposed at which the extrinsic base is formed. An alternative embodiment of the invention includes scaling the emitter contact by forming sidewall oxide filaments therewithin. A second layer of polysilicon is disposed thereover to form the emitter electrode, and to merge with the first layer to form the gates of the MOS transistors. Subsequent patterning and etching of the polysilicon, followed by sidewall filament formation and source/drain doping, is performed to complete the structure.
REFERENCES:
patent: 4346512 (1982-08-01), Ciang et al.
patent: 4475279 (1984-10-01), Gahle
patent: 4503603 (1985-03-01), Blossfeld
patent: 4529456 (1985-07-01), Anzai et al.
patent: 4616405 (1986-10-01), Yasuoka
patent: 4678936 (1987-07-01), Holloway
patent: 4707456 (1987-11-01), Thomas et al.
patent: 4710791 (1987-12-01), Shirato et al.
patent: 4737472 (1988-04-01), Schaber et al.
patent: 4752589 (1988-06-01), Schaber
patent: 4808548 (1989-02-01), Thomas et al.
patent: 4816423 (1989-03-01), Havemann
patent: 4818720 (1989-04-01), Iwasaki
patent: 4859630 (1989-08-01), Josquin
patent: 4877748 (1989-10-01), Havemann
patent: 4908324 (1990-03-01), Nihira et al.
patent: 4931407 (1990-06-01), Maeda et al.
patent: 4965220 (1990-10-01), Iwasaki
Ikeda, et al., "High Speed BiCMOS Technology with a Buried Twin Well Structure," IEEE Trans. Elec. Dev. vol. ED-34, No. 6 (Jun. 1987), pp. 1304-1309.
Chang, I., "FET-Bipolar Integration", IBM Technical Disclosure Bulletin, vol. 14, No. 1, Jun. 1971.
Eklund Robert H.
Prengle Scott H.
Braden Stanton C.
Chaudhuri Olik
Donaldson Richard L.
Fourson G.
Grossman Rene E.
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