Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Grooved and refilled with deposited dielectric material
Reexamination Certificate
2002-09-18
2004-06-29
Smith, Matthew (Department: 2825)
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
Grooved and refilled with deposited dielectric material
C438S128000, C438S299000, C438S587000, C438S595000, C438S745000
Reexamination Certificate
active
06756284
ABSTRACT:
TECHNICAL FIELD
The present invention relates to a method of forming a sublithographic opening in a layer of a material in a semiconductor process.
BACKGROUND OF THE INVENTION
Methods of forming a lithographic opening in a layer of a material in a semiconductor process are well known in the art. A lithographic opening is the smallest feature size in a semiconductor process that that process can produce. Thus, for example, in a 0.13 micron process, the smallest opening or feature size that the process can create would be an opening of 0.13 micron in size, which would be the lithographic feature for that process. A sublithographic opening would be an opening having dimensions that are smaller than the smallest feature size available for that lithographic process. Thus, any opening having a dimension less than 0.13 micron in a 0.13 micron process would be a sublithographic opening in a 0.13 micron process.
It is desirable in a lithographic process to form sublithographic openings in certain parts of the semiconductor structure to create a smaller feature size in order to handle problems such as misalignment or the like. In the prior art, it is known to create a sacrificial layer of a first material. A lithographic opening is created in the first layer of sacrificial material forming a lithographic opening therein. A second layer of a second material, different from the first material, is conformally deposited on the first layer. The second layer of the second material is then anisotropically etched until the first layer is reached. This creates spacers made of the second material in the opening in the first layer. The spacers in the opening of the first layer decreases the size of the opening thereby creating a sublithographic opening. The first layer of the first material along with the spacers of the second material is then used as a masking layer to create sublithographic openings in the layers upon which the first layer is deposited. See for example, U.S. Pat. No. 6,362,117. Such a process, however, requires the use of two layers of different materials to form a sacrificial masking layer. See also U.S. Pat. Nos. 6,365,451; 6,413,802; 6,429,125 and 6,423,475 on creation of sublithographic structures in a semiconductor structure.
SUMMARY OF THE INVENTION
A method of forming a sublithographic opening in a first layer of a first material in a semiconductor process comprises creating a lithographic opening on the first layer. The lithographic opening is over the location of the desired sublithographic opening. The first material in the lithographic opening is partially removed. A sacrificial layer is deposited conformally to the contour of the first layer over the first layer including over the lithographic opening. The sacrificial layer is also of the first material. The sacrificial layer and the first layer are anisotropically etched until all the material from the sublithographic opening is etched off to form the sublithographic opening within the lithographic opening.
The present invention also relates to another method of forming a sublithographic opening in a first layer of a first material in a semiconductor process. In the method, a sacrificial layer of a first material is deposited on a first layer. A lithographic opening is created on the sacrificial layer. The lithographic opening is positioned over the location of the desired sublithographic opening. The first material is removed in the lithographic opening. The first material is then laterally expanded by converting the first material to a second material thereby decreasing the size of the lithographic opening to a sublithographic opening. The first layer is then etched using the second material as a masking layer to form the sublithographic opening in the first layer.
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Office Action dated May 30, 2003 for patent application Ser. No. 10/246,882 for “Hybrid Trench Isolation Technology for High Voltage Isolation Using Thin Field Oxide In A Semiconductor Process”; Examiner: Stanetta D. Isaac; Art Unit 2812.
Anya Igwe U.
Gray Cary Ware & Freidenrich LLP
Silicon Storage Technology, Inc.
Smith Matthew
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