Method for forming a stress-free shallow trench isolation

Details Method for forming a stress-free shallow trench isolation Method for forming a stress-free shallow trench isolation

1998-01-28

2000-06-13

Dang, Trung

Semiconductor device manufacturing: process

Formation of electrically isolated lateral semiconductive...

Grooved and refilled with deposited dielectric material

438424, 438437, 438296, 438446, H01L 2176

Patent

active

060749326

ABSTRACT:
The method for forming a trench isolation includes the steps as follows. At first, a first pad layer is formed over the semiconductor substrate and a stacked layer is formed over the first pad layer. An opening is then defined in the first pad layer and the stacked layer. A portion of the first pad layer is removed to have an undercut region under the stacked layer. A second pad layer is formed on an exposed portion of the semiconductor substrate under the opening and the undercut region. Then a buffer layer within the undercut region and a sidewall structure on the stacked layer are formed. A portion of the second pad layer uncovered by the sidewall structure is removed. A portion of the semiconductor substrate uncovered by the stacked layer and the second pad layer is then removed to form a trench. A first insulator layer is formed over the trench and within the undercut region. Thus a trench structure with a first insulator layer can be formed.

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Andres Bryant et al., Characteristics of CMOS Device Isolation for the ULSI Age, 1994 IEEE, pp. 671-674.
S.E. Kim et al., Nitride Cladded Poly-Si Spacer LOCOS (NCPSL) Isolation Technology for the 1 Giga Bit DRAM, 1996 IEEE, pp. 825-828.
Pierre C. Fazan et al., A Highly Manufacturable Trench Isolation Process for Deep Submicron DRAMs, 1993 IEEE, pp. 57-60.

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