Method for forming a stacked capacitor of a DRAM cell

Details Method for forming a stacked capacitor of a DRAM cell Method for forming a stacked capacitor of a DRAM cell

1997-12-03

1998-10-20

Nguyen, Tuan H.

Semiconductor device manufacturing: process

Making passive device

Stacked capacitor

438253, 438255, 438398, H01L 2120

Patent

active

058245928

ABSTRACT:
A method for forming a capacitor of a dynamic random access memory cell is disclosed. The method includes forming a polysilicon layer (124) over a semiconductor layer, wherein at least a portion of the polysilicon layer is communicated to the substrate, and then patterning to etch a portion of the polysilicon layer. A mask layer (126) is formed on a portion of the polysilicon layer, and at least one silicon oxide region (128A) is formed in the polysilicon not covered by the mask layer. After etching a portion of the polysilicon layer using the silicon oxide region as an etch mask, a capacitor dielectric layer (136) is formed on the polysilicon layer, and a conductive layer (138) is formed on the capacitor dielectric layer.

REFERENCES:
patent: 5429980 (1995-07-01), Yang et al.
patent: 5656532 (1997-08-01), Tseng
patent: 5670406 (1997-09-01), Tseng
patent: 5723373 (1998-03-01), Chang et al.

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