Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Having air-gap dielectric
Reexamination Certificate
2003-09-09
2004-04-27
Niebling, John F. (Department: 2812)
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
Having air-gap dielectric
C438S245000, C438S246000, C438S360000, C438S361000, C438S388000, C438S389000, C438S407000, C438S409000, C438S411000, C438S423000, C438S429000, C438S430000, C438S431000, C438S432000, C438S524000
Reexamination Certificate
active
06727157
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a method for fabricating a semiconductor device; and, in particular, to a method for forming a shallow trench isolation (STI) which involves simplified processing steps while ensuring improved isolation through the use of an air gap.
DESCRIPTION OF THE PRIOR ART
Generally, semiconductor devices are fabricated through isolating active regions from field regions at a semiconductor substrate, and forming numerous devices such as transistors at the isolated active regions on the substrate.
In order to perform the device isolation, a shallow trench isolation STI technique has been widely used in the semiconductor device fabrication process. In the STI technique, shallow trenches are made at the semiconductor substrate, and filled with an insulating material. In this way, the field regions can be limited to the relatively narrow trench formation area while making it possible to miniaturize the device dimension as much as possible.
In a conventional STI process, in order to fabricate an STI having uniform width and depth, a variety of etch recipes have been widely used to minimize a leakage current.
FIGS. 1A
to
1
E sequentially illustrate the steps of fabricating the conventional STI.
Referring to
FIG. 1A
, a pad oxide layer
102
and a silicon nitride layer
104
are sequentially deposited. Next, a moat pattern
106
is formed on the silicon nitride layer
104
.
In
FIG. 1B
, the silicon nitride layer
104
, the pad oxide layer
102
and the silicon substrate
100
are sequentially etched through a photolithography technique using the moat pattern
106
as a mask to thereby form a STI region. At this case, the pad oxide layer
102
and the silicon nitride layer
104
is etched by controlling an etching selectivity and by monitoring an end point thereof using an end point detection system. The silicon substrate
100
is etched during a predetermined time. And then, the moat pattern
106
is stripped away.
Thereafter, the STI region is filled up with a SiO
2
to thereby form an insulation layer
108
as shown in FIG.
1
C.
As shown in
FIG. 1D
, the isolation layer
108
is then planarized through a chemical mechanical polishing (CMP) process. The CMP process is performed until a contact resistance of the silicon nitride layer
104
reaches a predetermined value.
Finally, the silicon nitride
104
is removed to thereby complete the STI process.
The conventional STI process is performed through only varying etching recipe in order to obtain a uniform STI depth.
However, as integration in semiconductor integrated circuits is higher, minimum feature size of the integrated circuits, often referred to as critical dimension (CD), is decreasing so that the STI space is also decreasing. For example, if CD of 0.18 um decreases to 0.15 um or 0.13 um, the STI space of 0.24 um is reduced to 0.21 um or 0.18 um. At this case, even if the etching recipe is varied in order to improve the uniformity of the STI depth, there are several limitations such as a reduction of a process margin, sophisticated polymer formation and the like.
Further, as shown in
FIG. 1D
, the CMP process has to be used in order to remove the overdeposited SiO
2
of the isolation layer
108
after the STI formation in the conventional STI process. When the isolation layer
108
is planarized through the CMP process, it is not easy to uniformly planarize because of fine STI space. In other words, difference of the STI space causes a generation of partially overpolished region to produce a step which affects a gate profile in a gate formation process.
Further, this CMP process also can make an overall STI fabricating process complex.
Therefore, there is a need to form STI having an uniform STI depth in a variety of STI space and simplify the overall STI fabricating process.
SUMMARY OF THE INVENTION
It is, therefore, an object of the present invention to provide a STI having an uniform STI depth in a variety of STI space and simplifying the overall STI fabricating process.
In accordance with the present invention, there is provided A method for fabricating a shallow trench isolation, comprising the steps of: sequentially depositing a silicon oxide layer, a silicon nitride layer and a moat pattern on a silicon substrate; etching the silicon nitride layer and the silicon oxide layer using the moat pattern as a mask to thereby partially expose the silicon substrate and then removing the moat pattern; performing ion implanting process into the silicon substrate using the silicon nitride layer as a mask, adjusting a dose of an implanted ion and an implant energy, to thereby form an isolation region; anodizing the isolation region to form a porous silicon and to form an air gap in the porous silicon, wherein a porosity of the porous silicon is determined by the dose of the implanted ion; oxidizing the porous silicon through an oxidation process; and removing the silicon nitride layer.
REFERENCES:
patent: 5098856 (1992-03-01), Beyer et al.
patent: 6406975 (2002-06-01), Lim et al.
patent: 6576558 (2003-06-01), Lin et al.
Anam Semiconductor Inc.
Isaac Stanetta
Niebling John F.
LandOfFree
Method for forming a shallow trench isolation using air gap does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method for forming a shallow trench isolation using air gap, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for forming a shallow trench isolation using air gap will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3262338