Semiconductor device manufacturing: process – Chemical etching – Combined with the removal of material by nonchemical means
Reexamination Certificate
2001-01-19
2002-08-06
Powell, William A. (Department: 1765)
Semiconductor device manufacturing: process
Chemical etching
Combined with the removal of material by nonchemical means
C216S038000, C216S088000, C438S719000, C438S723000, C438S724000, C438S745000
Reexamination Certificate
active
06429136
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a method for fabricating a semiconductor device, and more specifically to a method for forming a device isolation region of an STI (shallow trench isolation) structure in a semiconductor device.
With a recent elevated integration density in semiconductor devices, it has become indispensable to reduce device isolation region size. Therefore, the industry has begun to adopt an STI structure in the device isolation region, in place of a LOCOS (local oxidation of silicon) structure. In the STI structure of the device isolation region, after a trench is formed, an insulating film is formed on the whole surface, and then, the insulating film is etched back so that the insulating film remains in only the trench. However, when the insulating film is etched back, a recess is formed in the neighborhood of the trench because a step difference is generated between the surface of a semiconductor substrate and the remaining insulating film filled in the trench. Because of this recess, a problem has been encountered in which an etching residue of a gate electrode forming material is generated along an upper edge of the trench, and an inverse narrow width effect occurs.
A, typical countermeasure for solving this problem is disclosed in Japanese Patent Application Pre-examination Publication No. JP-A-10-050882.
Now, the typical countermeasure will be described with reference to
FIGS. 7A
to
7
D, which are diagrammatic sectional views illustrating the method disclosed in the above mentioned Japanese patent publication for forming the device isolation region of the STI structure in the semiconductor device.
On a principal surface of a silicon substrate
301
, a pad oxide film
302
is formed by a thermal oxidation, and then, a silicon nitride film
321
is deposited on the whole surface by a CVD (chemical vapor deposition) process. A patterned photoresist film
322
is formed on a surface of the silicon nitride film
321
. By using the patterned photoresist film
322
as a mask, the silicon nitride film
321
, the pad oxide film
302
and the silicon substrate
301
are etched in the named order by an anisotropic etching process, so that a trench
303
is formed on the principal surface of the silicon substrate
301
, as shown in FIG.
7
A.
Thereafter, the patterned photoresist film
322
is removed, and then, a silicon oxide based insulating film is formed on the whole surface. Furthermore, a first CMP (chemical mechanical polish) process is carried out by using the silicon nitride film
321
as a stopper, so that there remains an, insulating film
305
filling up the trench
303
, as shown in FIG.
7
B.
Then, the silicon nitride film
321
is selectively removed as shown in
FIG. 7C
, leaving a portion of insulating film
305
remaining above the surface of the silicon substrate
301
.
Succeedingly, a second CMP process is carried out using the silicon substrate
301
as a stopper, so that the pad oxide film
302
is removed and the insulting film
305
is partially removed, with the result that there remains an insulating film
305
A filling up the trench
303
, as shown in FIG.
7
D. Thus, a device isolation region
313
of the STI structure is formed.
According to the device isolation region forming method disclosed in the above mentioned Japanese patent publication, an upper surface of the insulting film
305
A and an upper surface of the silicon substrate
301
are substantially coplanar with each other at an upper end of the groove
303
, so that the generation of the above mentioned recess is avoided. As a result, the previously mentioned problem of etching residue of the gate electrode forming material along the upper edge of the trench and the inverse narrow width effect can be prevented.
In the device isolation region forming method disclosed in the above mentioned Japanese patent publication, however, since the second CMP process is carried out using the silicon substrate
301
as the stopper, the principal surface of the silicon substrate in active regions is exposed to the CMP process. As a result, the active region is contaminated with metallic ions contained in a slurry used in the CMP process, so that another problem is encountered in which the metallic ions give an adverse influence to the electrical characteristics of semiconductor circuit components formed at the principal surface of the silicon substrate. Furthermore, since the principal surface of the silicon substrate in the active regions becomes rough, it is necessary to carry out an additional planarization step for repairing the surface roughness.
BRIEF SUMMARY OF THE INVENTION
Accordingly, it is an object of the present invention to provide a method for fabricating a semiconductor device, which has overcome the above mentioned problems of the prior art.
Another object of the present invention is to provide a method for forming a device isolation region of the STI structure in a semiconductor device, without deteriorating the electric characteristics and requiring no additional planarization step.
The above and other objects of the present invention are achieved in accordance with the present invention by a method for forming a device isolation region of a shallow trench isolation structure in a semiconductor device, the method including the steps of:
forming a pad oxide film and a silicon nitride film on a principal surface of a silicon substrate in the named order, and forming a trench which penetrates through the pad oxide film and a silicon nitride film and extends from the principal surface of the silicon substrate into a body of the silicon substrate;
carrying out a second thermal oxidation to form a surface protecting oxide film on a surface of the trench;
depositing a first silicon oxide film on the whole surface to fill up the trench and to cover the silicon nitride film, and carrying out a first chemical mechanical polishing for the first silicon oxide film until the silicon nitride film is exposed;
selectively removing the silicon nitride film, and forming a silicon oxide protection film including the pad oxide film and having an increased film thickness sufficient to protect the principal surface of the silicon substrate in a later step;
depositing a second silicon oxide film on the whole surface;
carrying out a second chemical mechanical polishing for planarization, to remove at least a major portion of the second silicon oxide film from the principal surface of the silicon substrate but to maintain the principal surface of the silicon substrate in an non-exposed condition; and
carrying out a wet etching until the principal surface of the silicon substrate is exposed.
According to a first feature of the present invention, the silicon oxide protection film is formed by depositing a high-temperature oxide film on the whole surface including a surface of the pad oxide film.
According to a second feature of the present invention, the silicon oxide protection film is formed by carrying out a thermal oxidation to convert the pad oxide film into a thermal oxide film having an increased film thickness.
Specifically, according to the first feature of the present invention, there is provided a method for forming a device isolation region of a shallow trench isolation structure in a semiconductor device, the method including the steps of:
forming a pad oxide film on a principal surface of a silicon substrate by a first thermal oxidation, depositing a silicon nitride film on the whole surface, and carrying out an anisotropic etching using a patterned photoresist film formed on the silicon nitride film as a mask, to selectively remove the silicon nitride film and the pad oxide film and to form a trench in the principal surface of the silicon substrate;
carrying out a second thermal oxidation to form a surface protecting oxide film on a surface of the trench;
depositing a first silicon oxide film on the whole surface to fill the trench and to cover the silicon nitride film, and carrying out a first chemical mechanical polishing for the first silicon oxide
Hutchins, Wheeler & Dittmar
NEC Corporation
Powell William A.
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