Method for forming a shallow trench isolation structure

Semiconductor device manufacturing: process – Forming bipolar transistor by formation or alteration of... – Including isolation structure

Reexamination Certificate

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C438S435000

Reexamination Certificate

active

06329261

ABSTRACT:

BACKGROUND OF THE INVENTION
(a) Field of the Invention
The present invention relates to a method for forming a shallow trench isolation (STI) structure and, more particularly to a method for forming a SiO
2
film in a shallow trench.
(b) Description of the Related Art
Along with development of higher integration density and finer fabrication process for semiconductor devices, a STI technique has been increasingly used for isolation of transistor elements instead of the conventional LOCOS technique. The STI technique is described in 1996 VLSI technology symposium proceedings, pp 156, and 1996 IEDM technical proceedings, pp 841, for example. The STI technique is free from the problem of “bird's beak” extending in the horizontal direction as encountered in the LOCOS technique, thereby achieving a finer element isolation. In the current fabrication processes for semiconductor devices, the conventional LOCOS technique by which the silicon substrate is oxidized for forming a relatively pure silicon oxide film is used for the semiconductor devices of less precise design rule whereas the STI technique is used for the semiconductor devices of more precise design rule. In the STI technique, there are some problems associated with deposition of silicon oxide film in the trench formed on the silicon substrate.
Patent Publications JP-A-5-335290 and -5-335291 describe a STI technique wherein the silicon oxide film is deposited in the trench by a biased plasma-enhanced CVD process using a high-frequency power applied to the silicon substrate. In this technique, an electron-cyclotron-resonance (ECR) process generates high-density plasma for deposition of the silicon oxide film. The source gases generally used in the biased high-density plasma-enhanced CVD process include silane (SiH
4
), oxygen (O
2
) and argon (Ar). This technique takes advantage of the angle dependency of the etch rate at the slope in the sputter-etching process using argon ions by applying the high-frequency power to the substrate and of the high sputtering rate at the slope. More specifically, the silicon oxide film is deposited in a small-width trench while the silicon oxide film on the corner of a rectangular profile is removed by the sputter-etching technique using argon ions.
In the technique described in the publications mentioned above, the deposition and sputter-etching of the silicon oxide film occur concurrently, wherein a higher step coverage, and thus a higher film property, in the trench is achieved with a smaller ratio of deposited film to the sputter-etched film. In this case, however, the rate of the net deposited film decreases which is obtained by subtraction of the sputter-etched film from the gross deposited film. A smaller amount of the gross deposited film is achieved by decreasing the flow rate of silane, for example. On the other hand, a higher amount of sputter-etched film is achieved by increasing the high-frequency power applied to the substrate, for example. In either case, the decrease in the ratio of deposited film/sputter-etched film improves the step coverage in the trench.
After the silicon oxide film is deposited, the silicon oxide film is removed on the active region by a chemical-mechanical polishing (CMP) process. In the techniques described in both the publications, an additional step is interposed between the film deposition step and the CMP step for increasing the throughput and the reliability of the silicon oxide film.
There is a problem in the deposition process that the ECR-CVD system has an excessively large scale due to large dimensions of the plasma source. An inductively-coupled-plasma (ICP) system and a helicon-wave-excited plasma system are noticed and practically used instead of using the ECR plasma source for deposition of interlevel dielectric film on a metallic film. The source materials in the ICP system etc. are similar to those of the ECR-CVD system, and include silicon, oxygen and argon. To obtain a silicon oxide film having a stoichiometric SiO
2
structure requires 1.4 or higher for the flow rate ratio of O
2
/SiH
4
. A smaller flow rate ratio of O
2
/SiH
4
which is below 1.4 provides a silicon oxide film having a stoichiometrically silicon-rich structure, namely SiOx where x<2.
FIGS. 1A and 1B
consecutively show a fabrication process using a biased high-density-plasma-enhanced CVD technique. In this process, a silicon oxide film
402
is formed on a silicon substrate
401
by a thermal oxidation process, followed by deposition of a silicon nitride film
403
thereon. Subsequently, the silicon nitride film
403
, silicon oxide film
402
and silicon substrate
401
are selectively etched using a photolithographic technique and a dry etching technique to form a set of trenches
404
a
,
404
b
and
404
c
. Removal of the photoresist film after the formation of the trenches
404
a
,
404
b
and
404
c
provides the structure shown in FIG.
1
A.
A silicon oxide film
405
is then deposited in each trench and on the entire surface of the silicon substrate
401
by using a biased high-density-plasma-enhanced CVD process, as shown in FIG.
1
B. In this process, source gas including SiH
4
, O
2
and Ar is used wherein the flow rate ratio of O
2
/SiH
4
is above 1.5 to obtain a silicon oxide film having a stoichiometric SiO
2
structure. The silicon oxide film
405
is then subjected to a CMP process for planarization.
In the above process, there is a problem in that the silicon oxide film
405
often includes therein voids
406
a
and
406
b
, as shown in
FIG. 1B
, due to a high aspect ratio of the trenches
404
a
and
404
b
. The voids
406
a
and
406
b
do not disappear after the subsequent steps of fabrication, thereby degrading the performance of the semiconductor device. The voids are generally formed in the case of a smaller ratio of sputter-etched film to the gross deposited film in a high-density-plasma-enhanced CVD process wherein the substrate is applied with a high-frequency power. The voids are especially noticeable in a trench having a top opening of a 0.25 &mgr;m or less width and a high aspect ratio of 1.5 or more. In addition, the voids do not disappear after a heat treatment at a temperature of 1000° C. in a nitrogen ambient in the case of a silicon oxide film including substantially no impurities, such as phosphorus ions, and thus having an extremely higher glass softening temperature.
If the step coverage is to be improved for decreasing the voids by lowering the ratio of deposited film/sputter-etched film, the corners of the trench
406
a
or
406
b
including the silicon nitride films
503
a
to
503
c
, silicon oxide films
502
a
to
502
c
and the silicon substrate
501
are sputtered, as shown in
FIG. 2
, to have plasma damages
506
a
to
506
e
at the corners. The plasma damages
506
a
to
506
e
are generated due to the physical sputtering. Thus, the smaller ratio of deposited film/sputter-etched film improves the step coverage, and however increases the plasma damages and decreases the net deposition rate.
SUMMARY OF THE INVENTION
In view of the above, it is an object of the present invention to provide a method for forming a shallow trench used in a STI technique, which is capable of forming an excellent silicon oxide film in a trench having a small width and thus a high aspect ratio, substantially without forming a void in the resultant silicon oxide film and without damages to the underlying silicon substrate.
The present invention provides a method for forming a STI structure in a semiconductor device, including the steps of forming a trench on a semiconductor substrate, depositing a carbon-containing silicon oxide film in the trench, the silicon oxide film having a stoichiometric SiOxCy structure where x is below 2 and having a thickness which is larger than the depth of the trench, thermally treating the carbon-containing silicon oxide film to form a stoichiometric SiO
2
film, and polishing the SiO
2
film for planarization.
In accordance with the method of the present invention, when the carbon-containing silicon oxide

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