Method for forming a semiconductor device having a floating gate

Details Method for forming a semiconductor device having a floating gate Method for forming a semiconductor device having a floating gate

1995-10-17

1997-12-30

Niebling, John

Fishing, trapping, and vermin destroying

437 52, H01L 21265, H01L 218247

Patent

active

057029644

ABSTRACT:
A method for forming of a semiconductor device having a transistor with a floating gate includes the steps of forming a first insulating layer and a first conductive layer on a surface of the substrate, patterning the first conductive layer on a cell forming area to form preliminary floating gate electrodes and implanting ions on the cell forming area, forming a second insulating layer on the resulting surface so that the second insulating layer fills a space between the preliminary floating gate electrodes, forming a third insulating layer on the resulting surface, forming a second conductive layer on the third insulating layer, forming a fourth insulating layer on the second conductive layer, forming a gate electrode by patterning the fourth insulating layer and the second conductive layer, wherein the gate electrode pattern has a first distance between the gate lines in a portion to be a contact hole, and a second distance between the gate lines is arranged in another portion, the first distance being wider than the second distance, and forming a floating gate electrode by patterning the third insulating layer and the second conductive layer.

REFERENCES:
patent: 3984822 (1976-10-01), Simko et al.
patent: 4839705 (1989-06-01), Tigelaar
patent: 5070032 (1991-12-01), Yuan et al.

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