Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Of specified configuration
Reexamination Certificate
1999-05-12
2002-08-06
Wille, Douglas A. (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Of specified configuration
C257S751000, C257S753000, C257S768000
Reexamination Certificate
active
06429526
ABSTRACT:
STATEMENT REGARDING FEDERALLY SPONSORED RESEARCH OR DEVELOPMENT
Not. Applicable.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention is directed generally to semiconductor interconnections and a method for forming a semiconductor interconnect, such as a via or a contact, having an enlarged recess on its top surface.
2. Description of the Background
It is well known in the semiconductor art to use interconnects, known as vias and contacts, to connect an upper conductor of current, such as metal or polysilicon, through a dielectric layer to a lower conductor of current. A via is an electrical connection between two metal layers, and a contact, in contrast, is an electrical connection between anything other than two metal layers, such as between metal and silicon. Vias and contacts are used extensively in very large scale integrated circuits, with an average circuit containing 16 million vias and contacts.
Vias and contacts are formed by an opening in a dielectric layer and a conductor within the opening. Directional deposition methods, such as evaporation and sputtering, are often used to deposit the conductor within the opening. Such methods, however, often provide poor step coverage and only a thin conductive layer on the vertical wall of the opening. Thin layers are often not sufficient to provide good electrical contact between the upper and lower conductors, and result in a high resistance and a propensity for electromigration failures.
The problem of poor step coverage is exaggerated as the size of opening shrinks, and the aspect ratio increases. As the diameter of an opening approaches one micron, the aspect ratio typically approaches 1 to 1. To reliably obtain good electrical connection, the opening is usually partially or entirely filled with a conductor, known as a “plug”.
Prior art methods for forming a plug typically include tapering the top edge of the opening, followed by the formation of the plug in the opening, and concluding with a hydrofluoric acid bath. The tapering of the top edge is often accomplished with a sputter etch, and the purpose was to increase the surface area of the plug formed within the opening. The acid bath is used to clean the top surface of the dielectric layer, but it also dissolves some of the material at the interface between the plug and the dielectric layer, creating a small recess several hundred Angstroms deep around the top edge of the plug.
The prior art methods have several shortcomings, such as poor metal coverage over the interconnect due to the small recess, which often contains impurities that increase the contact resistance, and which may develop into a latent defect.
The latent defect may take the form of erosion of a top level conductor deposited on the recess, and can be triggered if contaminants in the recess are exposed to moisture in a subsequent processing step. In addition, residuals left on the surface of the wafer after the plug is formed may cause shorts between conductors on the wafer surface. Those residuals are often not removed by the hydrofluoric acid bath used in the prior art. Furthermore, when a sputter etch is used to taper the corners of the opening, particles sputtered from the top edge of the opening end up in the bottom of the opening. These are particles of the dielectric layer, so they are not good conductors of current, and they increase the contact resistance at the bottom of the opening. Additionally, silicon regions are often the lower conductor of an interconnect, and it is well known that sputtering damages and causes leakage in silicon. As a result, the prior art methods either risk damaging the silicon regions, or require several additional process steps to provide a protective coating on silicon prior to the sputtering, and to remove the protective coating after the sputtering.
Defects occur in about 1 in every 100 million contacts. Since the average semiconductor device contains about 16 million contacts, a defect may be expected in more than one in every seven devices. The defects may be a latent defect caused by contamination in the recess, poor contact or adhesion at the top of the connection, poor contact at the bottom of the connection caused, for example, by dielectric material present from the sputtering step, or damage to a silicon region at the bottom of the opening.
Thus, the need exists for an improved method of forming a connection having reduced contact resistance, improved contact adhesion, and decreased susceptibility to latent defects.
SUMMARY OF THE INVENTION
The present invention is directed generally to a method of forming a connection in an integrated circuit. The method includes the step of depositing a lower conductor. A dielectric layer is deposited on the lower conductor, with the dielectric layer having a lower surface adjacent to the lower conductor, and having an upper surface opposite the lower conductor. An opening extending between the upper surface and the lower surface of the dielectric layer is formed. A conductive plug is deposited within the opening. The plug has an upper surface proximate the upper surface of the dielectric layer. An edge of the upper surface is adjacent to the dielectric layer. A recess is formed proximate the edge of the upper surface. The recess extends into both the plug and the dielectric layer. Finally, an upper conductor is deposited on the upper surface of the dielectric layer and the upper surface of the plug.
The connection formed by the method of the invention is located within a dielectric layer of an integrated circuit, and is located between an upper conductor and a lower conductor. A conductive plug is located within the opening, with the plug having an upper surface proximate the upper conductor, and an upper edge where the upper surface is adjacent to the dielectric layer. A recess is located proximate the upper edge of the plug. The recess extends into both the plug and the dielectric layer.
The invention solves the above-mentioned shortcomings in the prior art by cleaning the recess of impurities, thereby reducing the risk of a latent defect. Furthermore, at the same time that the recess is formed, the edge of the upper surface may be tapered thereby increasing the surface area of the plug, increasing the adhesion by an upper conductor and decreasing the contact resistance. Finally, the invention eliminates the need for sputtering the dielectric layer prior to the formation of the plug, thereby eliminating a source of dielectric material in the bottom of the opening, and eliminating a potential source of damage to the lower conductor.
REFERENCES:
patent: 5567650 (1996-10-01), Straight et al.
patent: 5872053 (1999-02-01), Smith
patent: 5892285 (1999-04-01), Gonzalez et al.
Blalock Guy
Gonzalez Fernando
Prall Kirk
Doan Theresa T.
Micro)n Technology, Inc.
Wille Douglas A.
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