Method for forming a self-aligned isolation trench

Details Method for forming a self-aligned isolation trench Method for forming a self-aligned isolation trench

1997-12-05

1999-09-14

Chaudhuri, Olik

Semiconductor device manufacturing: process

Formation of electrically isolated lateral semiconductive...

Grooved and refilled with deposited dielectric material

438221, 438296, H01L 21762

Patent

active

059536217

ABSTRACT:
The present invention relates to a method for forming an isolation trench structure in a semiconductor substrate without causing deleterious topographical depressions in the upper surface thereof which cause current and charge leakage to an adjacent active area. The inventive method forms a pad oxide upon a semiconductor substrate, and then forms a nitride layer on the pad oxide. The nitride layer is patterned with a mask and etched to expose a portion of the pad oxide layer and to protect an active area in the semiconductor substrate that remains covered with the nitride layer. A second dielectric layer is formed substantially conformably over the pad oxide layer and the remaining portions of the first dielectric layer. A spacer etch is then carried out to form a spacer from the second dielectric layer. The spacer is in contact with the remaining portion of the first dielectric layer. An isolation trench etch follows the spacer etch. An optional thermal oxidation of the surfaces in the isolation trench may be performed, which may optionally be followed by doping of the bottom of the isolation trench to further isolate neighboring active regions on either side of the isolation trench. A conformal layer is formed substantially conformably over the spacer, over the remaining portions of the first dielectric layer, and substantially filling the isolation trench. Planarization of the conformal layer follows, either by CMP or by etchback or by a combination thereof. An isolation trench filled with a structure results. The resulting structure has a flange and shaft, the cross section of which has a nail shape in cross section.

REFERENCES:
patent: 3791882 (1974-02-01), Ogiue
patent: 4409609 (1983-10-01), Fukuda
patent: 4717682 (1988-01-01), Taka et al.
patent: 4819052 (1989-04-01), Hutter
patent: 4965221 (1990-10-01), Dennison et al.
patent: 5045904 (1991-09-01), Kobayashi et al.
patent: 5221857 (1993-06-01), Kano
patent: 5229316 (1993-07-01), Lee et al.
patent: 5387534 (1995-02-01), Prall
patent: 5433794 (1995-07-01), Fazan et al.
patent: 5541440 (1996-07-01), Kozai et al.
patent: 5780325 (1998-07-01), Lee
S. Wolf, Silicon Processing for the VLSI Era, Vol. 2; Process Integration, Lattice Press, pp. 54-56, 1990.
Stanley Wolf, Silicon Processing for the VLSI Era, vol. 2: Process Integration, Lattice Press, p. 331, 1990.
T. Ishijima, et al., "A Deep Sub-Micron Isolation Technology With T-Shaped Oxide (TSO) Structure," IEEE Publication No. Ch2865-4/90/0000-0257 (1990), pp. 257-260.

Affiliated with

Also associated with

Rating

Method for forming a self-aligned isolation trench does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method for forming a self-aligned isolation trench, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for forming a self-aligned isolation trench will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1519751