Method for forming a self-aligned bipolar transistor

Details Method for forming a self-aligned bipolar transistor Method for forming a self-aligned bipolar transistor

1990-12-19

1991-10-29

Hearn, Brian E.

Fishing, trapping, and vermin destroying

437 33, 437162, 437909, 437984, 148DIG11, 148DIG124, H01L 21265

Patent

active

050616463

ABSTRACT:
A structure and process for fabricating a fully self-aligned high-performance bipolar semiconductor device is disclosed. In accordance with one embodiment of the invention, a substrate is provided having a first surface. A heavily doped buried layer is formed in the substrate extending from the first surface and a lightly doped epitaxial layer overlies the first surface. An isolation region is formed in the epitaxial layer dividing the epitaxial layer into an active surface region and an isolation region. A base electrode is formed on a first portion of the active surface region having an opening which exposes a second portion of the active surface region. An emitter electrode, which is self-aligned to the base electrode, overlies a portion of the base electrode and extends through the opening in the base electrode making contact with the second portion of the active surface region. A collector plug is self-aligned to the active surface region at the edge of the base electrode and extends into the epitaxial layer making contact with the buried layer.

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patent: 4855801 (1989-08-01), Kuesters
patent: 4966865 (1990-10-01), Welch et al.
"An Advanced PSA Technology for High-Speed Bipolar LSI", H. Nakashiba et al., IEEE Transactions on Electron Devices, vol. ED27, No. 8, p. 1390, 1980.
"Submicron BiCMOS Well Design For Optimum Circuit Performance", R. A. Chapman et al., IEEE-IEDM Tech. Digest, p. 756, 1988.

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