Semiconductor device manufacturing: process – Making passive device – Stacked capacitor
Reexamination Certificate
1999-05-12
2001-12-11
Fahmy, Jr., Wael (Department: 2822)
Semiconductor device manufacturing: process
Making passive device
Stacked capacitor
C438S253000, C438S254000, C438S255000, C438S396000, C438S397000
Reexamination Certificate
active
06329264
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to the fabrication of a capacitor, and more particularly, to a method for forming a ragged polysilicon crown-shaped capacitor of a memory cell, such as a dynamic random access memory (DRAM) cell.
2. Description of the Prior Art
The increasing popularity of electronic equipment, such as computers for example, is increasing the demand for large semiconductor memories.
FIG. 1
shows a simplified diagram of the organization of a typical large semiconductor memory
14
. The storage cells of the memory
14
are arranged in an array including horizontal rows and vertical columns. The horizontal lines connected to all of the cells in the row are referred to as word lines
11
, and the vertical lines connected to all of the cells in the column are referred to as bit lines
13
. Data flows into and out of the cells via the bit lines
13
.
Row address
10
and column address
12
are used to identify a location in the memory
14
. A row address buffer
15
and a column address buffer
17
, respectively, receive row address
10
signals and column address
12
signals. The buffers
15
and
17
then drive these signals to a row decoder
16
and column decoder
18
, respectively. The row decoder
16
and the column decoder
18
then select the appropriate word line and bit line corresponding to the received address signal. The word and bit lines select a particular memory cell of the memory
14
corresponding to the received address signals. As is known in the art of semiconductor memory fabrication, the row decoder
16
and the column decoder
18
reduce the number of address lines needed for accessing a large number of storage cells in the memory
14
.
The array configuration of semiconductor memory
14
lends itself well to the regular structure preferred in “very large scale integration” (VLSI) ICs. For example, the memory
14
can be a dynamic random access memory (DRAM). DRAMs have become one of the most widely used types of semiconductor memory due to their low cost per bit, high device density and flexibility of use concerning reading and writing operations.
Early DRAMs used storage cells each consisting of three transistors and were manufactured using P type channel metal-oxide-semiconductor (PMOS) technology. Later, a DRAM storage cell structure consisting of one transistor and one capacitor was developed. A circuit schematic diagram corresponding to this structure is shown in FIG.
2
A. The gate of the transistor
20
is controlled by a word line signal, and data, represented by the logic level of a capacitor voltage, is written into or read out of the capacitor
22
through a bit line.
FIG. 2B
shows the cross section of a traditional one-transistor DRAM storage cell that uses a polysilicon layer
24
as one plate of the capacitor. The substrate region under the polysilicon plate
24
serves as the other capacitor electrode. A voltage can be applied to the plate
24
to store a logic value into the capacitor.
As the semiconductor memory device becomes more highly integrated, the area occupied by a capacitor of a DRAM storage cell typically shrinks. Thus, the capacitance of the capacitor is reduced owing to its smaller electrode surface area. However, a relatively large capacitance is required to achieve a high signal-to-noise ratio in reading the memory cell and to reduce soft errors (due to alpha particle interference). Therefore, it is desirable to reduce the cell dimension and yet obtain a high capacitance, thereby achieving both high cell integration and reliable operation.
One approach for increasing the capacitance while maintaining the high integration of the storage cells is directed toward the shape of the capacitor electrodes. In this approach, the polysilicon layer implementing the capacitor electrodes may have protrusions, fins, cavities, etc., to increase the surface area of the capacitor electrode, thereby increasing the storage capacitance while maintaining the small area occupied on the substrate surface. Consequently, this type of capacitor has come to be widely used in DRAM devices.
SUMMARY OF THE INVENTION
In accordance with the present invention, a method is provided for forming a ragged polysilicon crown-shaped capacitor, which substantially increases the surface area of the capacitor, for the construction of a memory cell, especially for a dynamic random access memory (DRAM) cell. In the preferred embodiment, a first dielectric layer is formed on a semiconductor substrate. A portion of the first dielectric layer is removed to define a contact hole within the first dielectric layer, wherein the contact hole is extended down to a source region in the substrate. Next, a conductive plug is formed to be communicated to the source region within the contact hole. A second dielectric layer is formed on the first dielectric layer and the conductive plug, and a third dielectric layer is formed on the second dielectric layer.
Next, portions of the third dielectric layer and the second dielectric layer are removed to define a storage node opening within the third dielectric layer and the second dielectric layer, wherein the storage node opening is located over the conductive plug. A first conductive layer is then formed to conformably cover the inside surface of the storage node opening and on the third dielectric layer. A hemispherical grained silicon layer is then formed on the first conductive layer. A fourth dielectric layer is formed on the substrate over the hemispherical grained silicon layer and the first conductive layer, and the substrate is planarized to the surface of the third dielectric layer. The fourth dielectric layer and the third dielectric layer are then removed to leave a storage node which is composed of the first conductive layer and the hemispherical grained silicon layer. Finally, a fifth dielectric layer is formed on the storage node, and a second conductive layer is then formed on the fifth dielectric layer to finish the capacitor structure.
REFERENCES:
patent: 5354705 (1994-10-01), Matthews et al.
patent: 5488011 (1996-01-01), Figura et al.
patent: 5518948 (1996-05-01), Walker
patent: 5763286 (1998-06-01), Figura et al.
patent: 5874334 (1999-02-01), Jenq et al.
patent: 5956587 (1999-09-01), Chen et al.
patent: 5963804 (1999-10-01), Figura et al.
patent: 6004857 (1999-12-01), Hsiao et al.
patent: 6010942 (2000-01-01), Chien et al.
Fahmy Jr. Wael
Thomas Toniae M.
TSMC-Acer Semiconductor Manufacturing Inc.
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