Method for forming a planarized integrated circuit

Details Method for forming a planarized integrated circuit Method for forming a planarized integrated circuit

1981-07-27

1985-01-08

Smith, John D.

Coating processes

Electrical product produced

Integrated circuit, printed circuit, or circuit board

204192D, 427 93, 427240, 427 99, H01L 21316

Patent

active

044927177

ABSTRACT:
A method is given for forming a planarized integrated circuit structure just prior to the formation of metallurgy interconnection lines on the integrated circuit. The method begins with the integrated circuit intermediate product having devices formed therein but before interconnection metallurgy has been formed on the principal surface of the product. A glass layer is deposited in a non-conformal way onto the principal surface of the integrated circuit. The glass is chosen to have a thermal coefficient of expansion that approximates that silicon and has a softening temperature of less than about 1200.degree. C. The thermal coefficient of expansion approximates that of silicon to reduce stress problems in the integrated circuit structure. The relatively low softening temperature is required for the next step of heating the structure to cause the flow of glass on the surface of the integrated circuit product to fill in the irregularities therein and to thereby planarize the integrated circuit surface. Openings are then formed through the glass down to the device elements of the integrated circuit. The interconnection metallurgy is formed over the surface of the glass and through the openings of the glass to interconnect the device elements of the integrated circuit. The glass may be deposited by various methods which include the sedimentation methods of spraying, centrifuging and spin-on plus sputtering or evaporation methods.

REFERENCES:
patent: 3804738 (1974-04-01), Lechaton et al.
patent: 3825442 (1974-07-01), Moore
patent: 3887733 (1975-06-01), Tolliver et al.
patent: 3899372 (1975-08-01), Esch et al.
patent: 3925572 (1975-12-01), Naber
patent: 3983022 (1976-09-01), Auyang et al.
patent: 4045594 (1977-08-01), Maddocks
patent: 4183135 (1980-01-01), Welling
patent: 4204894 (1980-05-01), Komeda et al.
patent: 4224089 (1980-09-01), Nishimoto et al.
patent: 4251571 (1981-02-01), Garbarino et al.
patent: 4271582 (1981-06-01), Shirai et al.
patent: 4305974 (1981-12-01), Abe

Affiliated with

Also associated with

Rating

Method for forming a planarized integrated circuit does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method for forming a planarized integrated circuit, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for forming a planarized integrated circuit will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-113318