Method for forming a phase change memory

Details Method for forming a phase change memory Method for forming a phase change memory

2002-07-19

2004-07-06

Lee, Eddie (Department: 2811)

Semiconductor device manufacturing: process

Making device or circuit responsive to nonelectrical signal

Responsive to electromagnetic radiation

C438S254000, C438S523000, C438S482000, C438S485000, C438S621000, C438S655000

Reexamination Certificate

active

06759267

ABSTRACT:

DESCRIPTION OF THE INVENTION
1. Field of the Invention
This invention pertains in general to a method for fabricating a semiconductor device and, more particularly, to a method for forming a phase change memory device.
2. Background of the Invention
The concept of using electrically erasable phase change materials, i.e., ones that can be electrically switched between amorphous and crystalline states, for a semiconductor memory device is known in the art as described in U.S. Pat. No. 3,271,591. Such phase change materials, for example, chalcogenide materials such as germanium, tellurium and selenium or combinations thereof, are capable of being switched between a first structural state, wherein the materials are generally amorphous, and a second structural state, wherein the materials are generally crystalline. The phase change materials may also be electrically switched between different detectable states from completely amorphous to completely crystalline states and states therebetween. Therefore, the materials may be switched in incremental steps. A phase change material also generally exhibits different electrical characteristics depending upon its state. For instance, the material may exhibit lower electrical resistivity in the crystalline state than in the amorphous state. Such a change in resistivity may be detected with known current sensing schemes, which, in turn, allows for the storage of “data” in the form of logic “0” or “1”.
In operation, the phase change material is capable of being transformed from a high resistance state to a low resistance state when a pulse of energy, known as “set pulse”, is applied to the material. The energy pulse causes at least a portion of the material to change from an amorphous state to a crystalline state. Additional set pulses may further crystallize the material, thereby decreasing the resistivity of the material.
In U.S. Pat. No. 4,599,705, entitled “Programmable cell for use in Programmable electronic arrays,” Holmberg et al., describes a programmable cell for use in programmable electronic arrays, such as PROM devices, logic arrays, gate arrays and die interconnect arrays. The programmable cell incorporates a phase change material having a highly non-conductive state settable and substantially non-resettable into a highly conductive state.
SUMMARY OF THE INVENTION
In accordance with the invention, there is provided a semiconductor device having a first memory cell that includes a substrate, an insulation layer disposed over the substrate, a first polysilicon gate formed over the insulation layer, at least one oxide spacer formed contiguous with one vertical sidewall of the first polysilicon gate, a silicide formed over a horizontal surface of the first polysilicon gate, a first phase change layer formed over a portion of the silicide, contiguous with the oxide spacer, and over a portion of the insulation layer, a first diffused region formed in the substrate, wherein the first phase change layer is formed above the first diffused region, and a second diffused region formed spaced-apart from the first diffused region in the substrate.
In one aspect, the device further includes a second memory cell that shares the second diffused region with the first memory cell.
Also in accordance with the present invention, there is provided a method for manufacturing a semiconductor device having an array of memory cells that includes providing a first transistor having first and second spaced-apart diffused regions, a first polysilicon gate, oxide spacers along vertical sidewalls of the first polysilicon gate, and a first silicide over a horizontal surface of the first polysilicon gate, providing a second transistor having second and third spaced-apart diffused regions, a second polysilicon gate, oxide spacers along vertical sidewalls of the second polysilicon gate, and a second silicide over a horizontal surface of the second polysilicon gate, wherein the first and second transistors share the second diffused region, providing a layer of phase change material over the first and second transistors, and defining and etching the phase change layer to form at least a first and second phase change layers, the first layer providing over the first transistor and the first diffused region, and the second layer providing over the second transistor and the third diffused region.
In one aspect, the method also includes providing an inter-layer dielectric over the first and second phase change layers and the first and second transistors, masking and etching through the inter-layer dielectric and the first and second phase change layers to form a plurality of vias, and filling at least one of the plurality of vias with a conductive material to form at least one plug to electrically connect one of the first and third diffused regions.
In another aspect, the method further includes providing an insulation layer over the inter-layer dielectric and the at least one plug, masking and etching through the insulation layer and inter-layer dielectric to form a second via, filling a conductive material in the second via to electrically connect the second diffused region, and providing an interconnect layer over the second via and the insulation layer.
Further in accordance with the present invention, there is provided a method of programming a first memory cell in an array of at least four memory cells in a semiconductor device, each memory cell including a polysilicon gate, first and second spaced-apart diffused regions, a silicide layer provided over the polysilicon gate, an oxide spacer provided contiguous with a vertical sidewall of the polysilicon gate, and a layer of phase change material provided over at least a portion of the silicide layer, contiguous with the oxide spacer, and over the first diffused region. The method includes electrically coupling the second diffused region of a first memory cell to a first bit line, electrically coupling the first diffused region of the first memory cell to a first word line, electrically coupling the second diffused region of a second memory cell to a second bit line, electrically coupling the first diffused region of the second memory cell to the first word line, electrically coupling the second diffused region of a third memory cell to the first bit line, electrically coupling the first diffused region of the third memory cell to a second word line, electrically coupling the second diffused region of a fourth memory cell to the second bit line, electrically coupling the first diffused region of the fourth memory cell to the second word line, and applying a high voltage pulse to the first word line and second bit line, and a low voltage pulse to the second word line and first bit line.
Additionally in accordance with the present invention, there is provided a method of reading a first memory cell in an array of at least four memory cells in a semiconductor device, each memory cell including a polysilicon gate, first and second spaced-apart diffused regions, a silicide layer provided over the polysilicon gate, an oxide spacer provided contiguous with a vertical sidewall of the polysilicon gate, a layer of phase change material provided over at least a portion of the silicide layer, contiguous with the oxide spacer, and over the first diffused region. The method includes electrically coupling the second diffused region of a first memory cell to a first bit line, electrically coupling the first diffused region of the first memory cell to a first word line, electrically coupling the second diffused region of a second memory cell to a second bit line, electrically coupling the first diffused region of the second memory cell to the first word line, electrically coupling the second diffused region of a third memory cell to the first bit line, electrically coupling the first diffused region of the third memory cell to a second word line, electrically coupling the second diffused region of a fourth memory cell to the second bit line, electrically coupling the first diffused region of the fourth memory cell to the second wor

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