Method for forming a multilayer integrated circuit

Details Method for forming a multilayer integrated circuit Method for forming a multilayer integrated circuit

1995-06-02

1997-02-18

Bowers, Jr., Charles L.

Fishing, trapping, and vermin destroying

437 56, 437915, H01L 218238, H01L 2184

Patent

active

056041373

ABSTRACT:
A multilayer semiconductor integrated circuit which does not suffer from latchup. The circuit comprises a semiconductor substrate, a first MOS transistor formed on the substrate, an interlayer insulator deposited on the first transistor, and a second MOS transistor formed on the interlayer insulator. The two transistors have different conductivity types. The gate electrode of the second transistor consists mainly of metal or metal silicide, e.g. aluminum. The upper and side surfaces of the gate electrode is coated with a material comprising an oxide of the metal or metal silicide.

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S. Wolf "Silicon Processing for the VLSI Era", vol. II, pp. 268-273, 568-583 Jun. 1990.

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