Semiconductor device manufacturing: process – With measuring or testing – Packaging or treatment of packaged semiconductor
Patent
1996-05-30
1997-08-12
Breneman, R. Bruce
Semiconductor device manufacturing: process
With measuring or testing
Packaging or treatment of packaged semiconductor
438109, 438458, H01L 21302
Patent
active
056565534
ABSTRACT:
A fabrication method and resultant monolithic electronic module comprising a plurality of stacked planar extending arrays of integrated circuit chips. The fabrication method includes dicing a wafer of integrated circuit chips into a plurality of arrays of integrated circuit chips. The arrays of integrated circuit chips are then stacked to form an electronic module. A metallization pattern may be deposited on a substantially planar surface of the electronic module, and used to interconnect the various arrays of integrated circuit chips contained therein. Specific details of the fabrication method and resultant multi-chip package are set forth.
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Leas James Marc
Voldman Steven Howard
Acosta Vanessa
Breneman R. Bruce
International Business Machines - Corporation
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