Method for forming a metallurgy system having a dielectric layer

Details Method for forming a metallurgy system having a dielectric layer Method for forming a metallurgy system having a dielectric layer

1994-09-16

1996-01-09

Fourson, George

Fishing, trapping, and vermin destroying

437195, 437235, H01L 21465

Patent

active

054829003

ABSTRACT:
A process where a blanket metal layer and a blanket SiO.sub.2 layer are formed on the surface of a semiconductor substrate. A metallurgy pattern is formed in the metal and SiO.sub.2 layers, and a thin conformal SiO.sub.2 layer formed over the metallurgy pattern. A relatively thick non-conformal SOG layer of insulating material is formed over the Si).sub.2 layer, which is etched back. Subsequently a relatively thick CVD layer is deposited on the surface. The steps are repeated to form additional metallurgy levels.

REFERENCES:
patent: 5344797 (1994-09-01), Pai et al.
patent: 5352630 (1994-10-01), Kim et al.
patent: 5366850 (1994-11-01), Chen et al.
Wolf et al., Silicon Processing for VLSI Era, vol. 1 Process Technology, pp. 161, 555-559, 1986 Lattice Press.
Wolf, Silicon Processing for the VLSI Era, vol. II Process Technology, pp. 214-217, 279-285, 1990, Lattice Press.

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