Semiconductor device manufacturing: process – Making passive device – Stacked capacitor
Reexamination Certificate
1999-08-20
2001-03-20
Bowers, Charles (Department: 2813)
Semiconductor device manufacturing: process
Making passive device
Stacked capacitor
Reexamination Certificate
active
06204144
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention provides a method of forming a capacitor, and more particularly, a method of forming a metal capacitor with two metal electrodes.
2. Description of the Prior Art
In the traditional manufacturing of an analog integrated circuit (IC) chip, top and bottom electrodes of a capacitor are usually made of two polysilicon layers. Since the two polysilicon layers will generate a deplete-region in low voltage operation and induce a serial parasitic capacitor to reduce the effective capacitance, such a capacitor with two polysilicon electrodes can't meet the requirement of low voltage coefficient of capacitance.
Recently, capacitors with two metal electrodes in place of two polysilicon electrodes have been disclosed to increase the capacitance of the capacitor. For example, U.S. Pat. No. 5,479,316 provides a method of forming a capacitor with two metal electrodes, wherein each electrode is made respectively of two metal layers. U.S. Pat. No. 5,086,370 also provides a method of forming a capacitor capable of low-voltage operation. A bottom electrode plate of a TiSi/Poly-Si layer and a top electrode plate of Poly-Si/TiSi layer are used in a capacitor to eliminate the deplete-region and meet the requirement of low voltage coefficient of capacitance.
However, while the requirement of low voltage coefficient of capacitance is met by the methods according to the prior art, either the manufacturing process is very complicated, or, at the very least, an extra metal layers is needed to construct the top/bottom electrodes, which results in a higher cost.
SUMMARY OF THE INVENTION
It is therefor a primary object of the present invention to solve the drawbacks in the methods according to the prior art by providing a method of forming a capacitor with two metal electrodes by patterning an existent metal layer for forming the top and bottom electrode plates.
In a first preferred embodiment, the present invention provides a method of forming a metal capacitor with two metal electrodes on a substrate of a semiconductor wafer. The semiconductor wafer comprises a gate area for a gate electrode, a source/drain area for a source/drain electrode, and a capacitor area for the metal capacitor. The method comprises the following steps of: (a) forming a first insulating layer to cover the substrate; (b) patterning the first insulating layer to format least a contact hole to expose the source/drain area; (c) conformably forming a barrier metal layer on the surface of the contact hole and the first insulating layer; (d) forming a metal plug in the contact hole; (e) forming a dielectric layer on the surface of the metal plug and the barrier metal layer; (f) patterning the dielectric layer to expose predetermined areas of the barrier metal layer to form a dielectric plate with a continuous vertical sidewall and an area larger than that of the capacitor area; (g) forming a metal layer on the surface of the dielectric plate, the metal plug and the barrier metal; (h) patterning the metal layer to expose the surface of the continuous vertical sidewall a predetermined area of the surface of the dielectric plate and predetermined areas of the surface of the first insulating layer to separately form a top electrode plate on the surface of the dielectric plate inside the capacitor area, a bottom electrode plate composed of the barrier metal layer under the dielectric plate, and a metal line; and (i) forming a second insulating layer for isolating the top electrode plate, the bottom electrode plate and the metal line.
In a preferred second embodiment, the present invention provides a method for forming a metal capacitor with two metal electrodes on a substrate of a semiconductor wafer. The semiconductor wafer comprises a plurality of conductive-metal lines and a capacitor area for the metal capacitor. The method comprises the following steps of: (a) forming a first insulating layer for covering the substrate; (b) patterning the first insulating layer to form at least a via hole to expose a portion area of the conductive-metal lines; (c) conformably forming a barrier metal layer on the surface of the via hole and the first insulating layer; (d) forming a metal plug in the via hole; (e) forming a dielectric layer on the surface of the metal plug and the barrier metal layer; (f) patterning the dielectric layer to expose predetermined areas of the barrier metal layer to form a dielectric plate with a continuous vertical sidewall and an area larger than that of the capacitor area; (g) forming a metal layer on the surface of the dielectric plate, the metal plug and the barrier metal; (h) patterning the metal layer to expose the surface of the continuous vertical sidewall, a predetermined area of the surface of the dielectric plate and predetermined areas of the surface of the first insulating layer to separately form a top electrode plate on the surface of the dielectric plate inside the capacitor area, a bottom electrode plate composed of the barrier metal layer under the dielectric plate, and a metal line; and (i) forming a second insulating layer for isolating the top electrode plate, the bottom electrode plate and the metal line.
It is an advantage of the present invention that no extra metal layer need to be formed in the present invention in comparison with that in the traditional metal-connection process. Therefor an economic integrated process flow of forming a metal capacitor with two metal electrodes is achieved.
This and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after having read the following detailed description of the preferred embodiment which is illustrated in the various figures and drawings.
REFERENCES:
patent: 5086370 (1992-02-01), Yasaitis
patent: 5479319 (1995-12-01), Smrtic et al.
Bowers Charles
Fish & Richardson P.C.
Thompson Craig
United Microelectronics Corporation
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