Method for forming a linear heterojunction field effect transist

Details Method for forming a linear heterojunction field effect transist Method for forming a linear heterojunction field effect transist

1994-04-18

1996-01-09

Nguyen, Tuan H.

Fishing, trapping, and vermin destroying

437 44, 437133, 437912, 148DIG72, H01L 21335

Patent

active

054828759

ABSTRACT:
A low power heterojunction field effect transistor (10, 30, 50, 60) capable of operating at low drain currents while having a low intermodulation distortion. A channel restriction region (9, 38, 51) is formed between the gate electrodes (24, 41, 69) and the drain electrodes (25, 46, 65). The channel restriction region (9, 38, 51) depletes the channel layer (13, 33) thereby constricting a channel and lowering a drain saturation current. The channel restriction region (9, 38, 51) may be used to set a desired drain saturation current such that a second derivative of the transconductance with respect to the gate-source voltage is approximately zero and a first derivative of the transconductance with respect to the gate-source voltage is, approximately, a relative maximum at the desired operating point.

REFERENCES:
patent: 5141879 (1992-08-01), Goronkin et al.
patent: 5180681 (1993-01-01), Mishra et al.

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