Method for forming a horizontal self-aligned transistor

Details Method for forming a horizontal self-aligned transistor Method for forming a horizontal self-aligned transistor

1990-07-05

1991-05-28

Hearn, Brian E.

Fishing, trapping, and vermin destroying

437157, 437158, 437 63, 148DIG150, H01L 21265

Patent

active

050195255

ABSTRACT:
A method for forming a self-aligned horizontal transistor includes the step of first defining a narrow base contact on an isolated N-tank (10) to define a first reference edge (41). A layer of sidewall oxide (40) is then disposed on the vertical wall of the base contact (34) to define a second reference edge (42). An emitter well (44) and a collector well (46) are then defined on either side of the contact with the vertical wall of the emitter well (44) aligned with the reference edge (42). A dopant material is then disposed adjacent the reference edge (42) and the dopant diffused into the substrate from a lateral direction to form a P-type base region (58) with a graded impurity profile. N-doped regions (64) and (66) are then formed in the emitter and collector wells to form the emitter and collector of the transistor.

REFERENCES:
patent: 4050965 (1977-09-01), Ipri et al.
patent: 4277883 (1981-07-01), Kaplan
patent: 4447823 (1984-05-01), Maeguchi et al.
patent: 4545113 (1985-10-01), Vora
patent: 4743565 (1988-05-01), Goth et al.
patent: 4897698 (1990-01-01), Zorinsky et al.

Affiliated with

Also associated with

Rating

Method for forming a horizontal self-aligned transistor does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method for forming a horizontal self-aligned transistor, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for forming a horizontal self-aligned transistor will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-35845