Semiconductor device manufacturing: process – Making passive device – Stacked capacitor
Patent
1999-05-12
2000-09-05
Monin, Jr., Donald L.
Semiconductor device manufacturing: process
Making passive device
Stacked capacitor
438396, 438255, H01L 2120
Patent
active
06114214&
ABSTRACT:
A double-crown rugged polysilicon capacitor of a dynamic random access memory cell is formed. A second dielectric layer is formed on a first dielectric layer, followed by the formation of a first conductive layer on the second dielectric layer. Portions of the first conductive layer and the second dielectric layer are removed to define an opening. A second conductive layer is formed within the opening and on the first conductive layer. A sidewall structure is formed within the opening on sidewalls of the second conductive layer. Next, a removing step is performed to remove a portion of the second conductive layer which is uncovered by the sidewall structure. The sidewall structure and a portion of the first dielectric layer are removed, using the residual second conductive layer as a mask, to define a contact hole within the first dielectric layer. A third conductive layer fills up the contact hole. Portions of the first conductive layer and the third conductive layer uncovered by the patterning layer are then removed. Conductive sidewalls are formed on sidewalls of the patterning layer, the first conductive layer and the third conductive layer. The patterning layer and the second dielectric layer are then removed to leave a storage node composed of the first conductive layer, the second conductive layer, the third conductive layer, and the conductive sidewalls.
REFERENCES:
patent: 5693554 (1997-12-01), Lee
patent: 5851878 (1998-12-01), Huang
Monin, Jr. Donald L.
Peralta Ginette
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