Semiconductor device manufacturing: process – Chemical etching – Vapor phase etching
Patent
1999-04-28
2000-08-29
Powell, William
Semiconductor device manufacturing: process
Chemical etching
Vapor phase etching
423734, 423738, 423743, 423717, H01L 2100
Patent
active
061108375
ABSTRACT:
The present invention discloses a method for forming hard mask of half critical dimension on a substrate. A substrate is provided for the base of integrated circuits. A silicon oxide layer is formed on the substrate. A photoresist layer is formed on the silicon oxide layer and it is has a critical dimension, which the conventional lithography process can make. Subsequently, a hard mask of half critical dimension is formed in the silicon oxide layer by using the photoresist layer as an etching mask. After the oxide hard mask is formed, the gate structure of half critical dimension is formed by using the oxide hard mask.
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patent: 5776836 (1998-07-01), Sandhu
patent: 5902133 (1999-05-01), Linliu
patent: 5916821 (1999-06-01), Kerber
patent: 5965461 (1999-10-01), Yang et al.
patent: 6020269 (2000-02-01), Wang et al.
Chan Bor-Wen
Linliu Kung
Powell William
Worldwide Semiconductor Manufacturing Corp.
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