Semiconductor device manufacturing: process – Chemical etching – Vapor phase etching
Reexamination Certificate
2001-08-27
2004-04-06
Coleman, W. David (Department: 2823)
Semiconductor device manufacturing: process
Chemical etching
Vapor phase etching
C438S717000, C438S720000, C438S722000, C438S737000
Reexamination Certificate
active
06716760
ABSTRACT:
BACKGROUND
1. Technical Field
A high integration semiconductor device is disclosed, and in particular, a method for forming a gate electrode of such a high integration semiconductor device is disclosed in which an etch prevention layer is formed between the nitride layer and the anti-reflection layer in order to prevent the nitride layer from over-etching, thereby preventing generation of a leakage current, caused by a bridge formed between the gate and a bit line.
2. Description of the Background Art
In general, the most widely used gate electrode in semiconductor devices is a doped polycrystalline silicon. As higher integration of semiconductor devices are being developed, metallic layers of titanium and tungsten are also widely used.
While the gate electrode using polycrystalline silicon has the advantage of ensuring stability of the process, its high specific resistance causes reduction of the design rule, thus hindering improvement of the operational speed.
In order to solve this problem, a method has been introduced using, as a gate electrode, a refractory metal such as tungsten with a low specific resistance.
On the other hand, in recent years, a high integration semiconductor device (1 Giga grade) with its gate electrode line width of 0.13 &mgr;m has been fabricated and put to practical use. Therefore, as a conductive layer of a gate electrode, a process for using the polysilicon layer and the tungsten layer, as compound, has been introduced.
FIGS. 1
a
to
1
d
are views illustrating sequential processes for fabricating a high integration semiconductor device in accordance with the conventional art.
As shown in
FIG. 1
a,
a gate oxide
1
a,
a poly silicon layer
2
, a tungsten nitride layer
3
, a tungsten layer
4
, a nitride layer
5
and an anti-reflection layer
6
are sequentially deposited on a semiconductor substrate
1
.
Thereafter, as shown in
FIG. 1
b,
after depositing a photoresist layer on the resultant material, a photoresist pattern
7
is formed in order to intercept the part to be formed a gate.
Thereafter, as shown in
FIG. 1
c,
after removing the photoresist pattern
7
, the anti-reflection layer
6
, the nitride layer
5
, the tungsten layer
4
, the tungsten nitride layer
3
are sequentially etched.
At this time, a gas containing fluorine is commonly used as an etching gas for etching the anti-reflection layer
6
, the nitride layer
5
, the tungsten layer
4
and the tungsten nitride layer
3
.
As shown in
FIG. 1
d,
the polysilicon layer
2
is etched in order to expose the semiconductor substrate
1
.
However, as mentioned above, as shown in
FIG. 1
c,
when etching the photoresist pattern
7
, the anti-reflection layer
6
and the lower gate layer, the entire thickness loss of the anti-reflection layer
9
and the nitride layer
8
is about 1000 Å as represented with phantom lines and, at this time, the thickness of the tungsten layer
4
and the tungsten nitride layer
3
is about 700 Å.
Accordingly, in the next processes, when etching the self align contact (SAC), there is a disadvantage that since the thickness of the hard mask nitride layer
5
is thin, a bridge between the gate and the bit line is formed, thereby generating a leakage current. Although it is possible to increase the thickness of the hard mask nitride layer
5
in order to solve the above disadvantage, an etching selectivity to the photoresist layer becomes lower when etching the gate because of the increase in the thickness of the hard mask nitride
5
, thereby generating a notch and a top loss.
In addition, when etching the tungsten layer
4
and the tungsten nitride layer
3
, a difference in the thickness of the nitride layer
3
occurs because of the difference of the etching speed of the etching device.
SUMMARY OF THE DISCLOSURE
Accordingly, a method for forming a gate of a high integration semiconductor device is disclosed wherein when forming a gate electrode on a semiconductor substrate by depositing a nitride layer and an anti-reflection layer after depositing a conductive layer constructed by a gate oxide layer, a polysilicon layer, a tungsten nitride layer and a tungsten layer, an etch prevention layer is formed between the nitride layer and the anti-reflection layer in order to prevent the nitride layer from over-etching, thereby preventing the leakage current, caused by a bridge formed between the gate and the bit line.
In one aspect of the disclosed method, in a gate structure of the high integration semiconductor device constructed with a gate oxide layer, a polysilicon layer, a tungsten layer, a tungsten nitride layer, a nitride layer and an anti-reflection layer, which are sequentially formed on the semiconductor substrate, the gate structure comprises an etching prevention layer for preventing etching of the tungsten layer and the tungsten nitride layer between the anti-reflection layer and the nitride layer.
One disclosed method for forming a gate of a high integration semiconductor device comprises: forming a gate oxide layer, a polysilicon layer, a tungsten nitride layer, a tungsten layer, and a nitride layer on a semiconductor substrate; depositing an etching prevention layer and an anti-reflection layer sequentially on the resultant material; forming a pattern by depositing a photoresist layer on the anti-reflection layer and executing a mask process; etching the nitride layer, the tungsten layer and the tungsten nitride layer sequentially with an etching gas comprising fluorine after performing the above process; and etching the etching prevention layer and the polysilicon layer through an etching gas comprising chlorine after performing the above process.
Preferably, the etching prevention layer has a thickness ranging from about 50 to about 1000 Å.
The etching gas comprises fluorine in the form of any one of NF
3
, SF
6
and CF
4
gases.
REFERENCES:
patent: 5869901 (1999-02-01), Kusuyama
patent: 6074905 (2000-06-01), Hu et al.
patent: 6187686 (2001-02-01), Shin et al.
Stanley Wolf Ph.D. and Richard N. Tauber Ph.D. in Silicon Processing for the VLSI Era, vol. 1: Process Technology, Lattice Press, 1986, pp. 539-542, 581-582.
Bae Young-hun
Park Won-sung
Brewster William M.
Coleman W. David
Hynix Semiconductor Inc
Marshall & Gerstein & Borun LLP
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