Fishing – trapping – and vermin destroying
Patent
1990-09-21
1991-05-28
Hearn, Brian E.
Fishing, trapping, and vermin destroying
437240, 437922, 437985, 437 60, 437919, 437191, 148DIG55, 357 51, H01L 2944
Patent
active
050195328
ABSTRACT:
A method for forming a fuse for integrated circuits and a fuse produced therefrom is disclosed. The fuse (10) includes a substrate (12) having thick oxide layers (14) with a gap (16) formed therebetween. A second oxide layers (20), (14) is grown onto an N+ region (18). At the intersection between oxide layer (20), a sublithographic area is exposed and a dielectric layer (24) is formed therein. This structure is capable of reducing the capacitance between a polysilicon layer (26) formed thereon and the N+ diffusion region (18).
REFERENCES:
patent: 4598462 (1986-07-01), Chandrasekhar
patent: 4635345 (1987-01-01), Hankins et al.
patent: 4823181 (1989-04-01), Mohsen et al.
patent: 4876220 (1989-10-01), Mohsen et al.
Esmat Handy, John McCollum, Shih-ou Chen, Steve Chiang, Shafy Eltoukhy, Jim Chang; Ted Speers, Amr Mohsen, "Dielectric Based Antifuse for Logic and Memory ICs", IEEE, 1988, 786-789.
Brady III W. James
Comfort James T.
Fleck Linda J.
Hearn Brian E.
Sharp Melvin
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