Active solid-state devices (e.g. – transistors – solid-state diode – Integrated circuit structure with electrically isolated... – With contact or metallization configuration to reduce...
Reexamination Certificate
1998-09-30
2001-10-09
Meier, Stephen D. (Department: 2822)
Active solid-state devices (e.g., transistors, solid-state diode
Integrated circuit structure with electrically isolated...
With contact or metallization configuration to reduce...
C257S621000
Reexamination Certificate
active
06300666
ABSTRACT:
CROSS REFERENCE TO RELATED APPLICATIONS
Not applicable.
U.S. GOVERNMENT RIGHTS
Not applicable.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to device processing of Silicon-On-Insulator (SOI) wafers, and more particularly, relates to a method of forming a frontside contact to the silicon substrate of a SOI wafer.
2. Description of the Prior Art
SOI Technology has been shown to provide many advantages over bulk silicon technology. These advantages include higher speed, lower power and resistance to certain forms of radiation.
In many applications it is desirable to ground or bias the bottom substrate of a SOI circuit. In order to make an electrical connection at the backside of the wafer it requires additional wafer processing. In most of the more advanced packaging technologies such as flip chip and die stacking, making a connection to substrate silicon via the back of the die is cost prohibitive. Therefore, connecting the substrate to a standard topside metallization pad is necessary. However, the challenge of forming this contact during normal processing flow without adding major requirements to the standard processes without this topside contact is significant. This is especially true in the presence of highly planarized contact dielectric processes (i.e. Chemical Mechanical Polishing (CMP) and photoresist planarized contacts) required for today's deep submicron lithography where the thickness of the contact dielectric over the substrate contact may be in the range of 0.2 to 1.0 micron more than the thickness over the thickest region in the normal circuit area, which would typically be the source/drain contact areas. Scaling designs into the deep submicron range normally requires a high degree of planarity in the contact dielectric in order to be able to lithographically define contact and metal interconnect layers. Even without a frontside contact to the substrate, the selectivity of the contact etch is already required to be quite high. In the prior art, in order to make simultaneous contact to gate polysilicon, source and drain regions, and the underlying substrate, the selectivity of contact etch to gate polysilicon must be increased significantly in order to be able to etch the planarized contact dielectric all the way down to the silicon substrate.
Brady, et al, in U.S. Pat. No. 5,314,841, “Method of Forming a Frontside Contact to the Silicon Substrate of a SOI Wafer” describes a frontside contact formation process. This prior art has the weakness of increasing the etch selectivity requirements of the process significantly when compared to a process that does not include the frontside substrate contact.
It is therefore an object of the present invention to provide a frontside substrate contact without significantly increasing the selectivity requirements of the etch of the planarized contact dielectric.
It is another object of the present invention to teach a simple method to create a sloped oxide edge using reflowed photoresist with an oxide etch non-selective to photoresist.
BRIEF SUMMARY OF THE INVENTION
The present invention solves these and other needs by providing a method which both forms the substrate contact as part of the normal processing sequence without exposing the substrate silicon to the gate etch and uses a local interconnect to raise said substrate contact to a level above the source/drain areas prior to depositing the contact dielectric. It is assumed in the process flow stated below that the top silicon is removed at some time prior to Step
2
.
1. Proceed with standard device processing steps up through gate etch.
2. Define a substrate contact region with photoresist.
3. Bake the photoresist to create a positive edge profile.
4. Etch a hole or trench down to the substrate through the exposed hole in the photoresist.
5. Remove the photoresist and continue with normal processing.
6. Cover the substrate contact region while implanting a dopant of the opposite type as the substrate.
7. Open the substrate contact region while implanting a dopant of the same type as the substrate.
8. Open the substrate contact region for normal silicidation.
9. Deposit and define a local interconnect from the silicide region within the substrate contact region up to the top of the oxide layers.
10. Deposit and planarize a contact dielectric.
11. Within normal metalization processing, etch through the planarized contact dielectric down to the top end of the local interconnect, as well as the source, drain, and gate contact locations.
REFERENCES:
patent: 4549927 (1985-10-01), Goth et al.
patent: 4873204 (1989-10-01), Wong et al.
patent: 5079605 (1992-01-01), Blake
patent: 5314841 (1994-05-01), Brady et al.
patent: 5445988 (1995-08-01), Schwalke
patent: 5565236 (1996-10-01), Gambino et al.
patent: 5574298 (1996-11-01), Hashimoto et al.
patent: 5610083 (1997-03-01), Chan et al.
patent: 5814848 (1998-09-01), Oshima
patent: 5945712 (1999-08-01), Kim
patent: 6002154 (1998-07-01), Fujita
Dougal Gregory D.
Fechner Paul S.
Golke Keith W.
Fredrick Kris T.
Honeywell Inc.
Meier Stephen D.
Vockrodt Jeff
LandOfFree
Method for forming a frontside contact to the silicon... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method for forming a frontside contact to the silicon..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for forming a frontside contact to the silicon... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2617442