Semiconductor device manufacturing: process – Chemical etching – Vapor phase etching
Reexamination Certificate
2005-04-19
2005-04-19
Nhu, David (Department: 2818)
Semiconductor device manufacturing: process
Chemical etching
Vapor phase etching
C438S700000
Reexamination Certificate
active
06881678
ABSTRACT:
In a method for forming a dual damascene structure in a semiconductor device, an insulating layer is formed on a semiconductor substrate and a silicon nitride etch stop layer is formed on the insulating layer. Then a photoresist layer is applied on the etch stop layer for a contact hole pattern. Thereafter, the insulating layer is etched according to the contact hole pattern and the rest etch stop layer is pull back etched to expose upper surface of the insulating layer. The insulating layer is etched again according to the modified pattern of the rest etch stop layer and the rest etch stop layer is removed so that a dual damascene structure is completed. Therefore, a dual damascene structure can be made by using a single photoresist process and a single etch stop layer so that a manufacturing process is simplified.
REFERENCES:
patent: 6383919 (2002-05-01), Wang et al.
patent: 6457477 (2002-10-01), Young et al.
patent: 6743713 (2004-06-01), Mukherjee-Roy et al.
patent: 6797633 (2004-09-01), Jiang et al.
Anam Semiconductor Inc.
Fortney Andrew D.
Nhu David
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