Coating processes – Electrical product produced – Integrated circuit – printed circuit – or circuit board
Patent
1973-12-19
1976-01-20
Pitlick, Harris A.
Coating processes
Electrical product produced
Integrated circuit, printed circuit, or circuit board
118 48, 118 49, 118 491, 118 495, 427248, 427294, 427299, C23C 1108
Patent
active
039340600
ABSTRACT:
The present invention is directed to a method for forming a thin silicon dioxide deposited layer on a semiconductor structure. The silicon dioxide layer is formed in a hot wall furnace typically used for diffusions. A convenient temperature is selected from those which are suitable for decomposing the TEOS source of the silicon dioxide into its constituent parts out of which the silicon dioxide layer is formed. A vacuum is used to pull the TEOS gas through the diffusion tube. Care is exercised to assure that the flow of the TEOS material through the diffusion tube is kept at a constant rate. Prior to the first use of a new TEOS source bottle, the bottle is placed in a vacuum at least low enough to complete the boiling of impurities from the source material. This predeposition vacuum step is calculated to remove all the impurities contained in the source bottle and caused by the in situ decomposition of the source material during transit and storage. Whenever the source material is allowed to stand for any period of time; i.e., overnight or any number of hours, the predeposition vacuum step removes those impurities formed during the in situ decomposition of the source material since its last use.
Wafers to be coated with a deposited oxide layer are placed in a furnace boat perpendicular to the flow of the source gas. In the preferred embodiment, the wafers are spaced 200 mils apart. While there is no indentified maximum distance between wafers at which the present invention ceases to operate successfully, undesirable results occur by placing adjacent wafers closer than 100 mils while acceptable results are achieved by placing the wafers 100-200 mils apart.
REFERENCES:
patent: 3408224 (1968-10-01), Ashburn et al.
patent: 3409483 (1968-11-01), Watson
patent: 3445280 (1969-05-01), Tokuyama et al.
patent: 3755890 (1973-09-01), Klehm
Perrault et al., "Coating Process," IBM Technical Disclosure Bulletin, Vol. 16, No. 3, Aug. 1973, p. 726.
Burt Dan L.
Taraci Richard F.
Zavion John E.
Motorola Inc.
Pitlick Harris A.
Trevors Ellen P.
Weiss Harry M.
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