Semiconductor device manufacturing: process – Making passive device – Stacked capacitor
Reexamination Certificate
1999-01-29
2002-07-02
Nguyen, Tuan H. (Department: 2813)
Semiconductor device manufacturing: process
Making passive device
Stacked capacitor
C438S255000
Reexamination Certificate
active
06413833
ABSTRACT:
BACKGROUND OF THE INVENTION
(a) Field of the Invention
The present invention relates to a method for forming a CVD silicon film on a semiconductor wafer and, more particularly, to a method suitable for use in forming a cylindrical electrode of a memory capacitor in a memory cell of a semiconductor memory device.
(b) Description of the Related Art
Recently, there is a request for increasing the electrostatic capacitance per unit area of the capacitor of a memory cell in a semiconductor memory device such as DRAM (Dynamic Random Access Memory). Either a top electrode or a bottom electrode, for instance a bottom electrode, is formed of a cylindrical shape to meet the request for the increase of the capacitance. In addition, it is also attempted to form a hemispherical grained silicon (HSG-Si) structure on the cylindrical electrode for further increasing the surface area of the cylindrical electrode.
Patent Publication JP-A-9-167833 proposes a first conventional process for forming the HSG-Si structure on the electrode surface. The proposed process includes the step of forming seeds for the HSG-Si on the surface of the cylindrical bottom electrode by a low-pressure chemical vapor deposition (LPCVD) process, followed by selective ion etching using the seeds as a mask to enlarge the roughness of the HSG-Si on the surface, thereby increasing the surface area of the cylindrical bottom electrode. The etching process is conducted while changing the incident angle of the etching gas, which involves a complicated process.
A second conventional process is also known which may replace the complicated first conventional process. The second conventional process includes the step of introducing silane gas (including disilane gas) into a HSG reactor receiving therein semiconductor wafers having bottom electrodes, followed by a heat treatment at a predetermined temperature, thereby forming HSG-Si structure on the bottom electrode.
Although the second conventional process has an advantage of simplified process, the bottom electrode manufactured by the second conventional process has larger surfaces of the HSG (grains) on the outer surface of the bottom electrode compared to the inner surface thereof. The larger surfaces of the HSG do not effectively increase the surface area of the bottom electrode due to the contact between the surfaces of the HSG.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide a method for forming a CVD silicon film which can be formed as a cylindrical electrode having a suitable HSG-Si structure, which is capable of increasing the capacitance of the memory cell capacitor.
The present invention provides a method for manufacturing a semiconductor device comprising the steps of consecutively introducing phosphine gas and silane gas onto a surface of a semiconductor wafer to deposit a CVD silicon film thereon, and heat treating the CVD silicon film. Instead of consecutively introducing phosphine gas and silane gas, a mixture of phosphine gas and silane gas may be introduced.
The present invention also provides a method for manufacturing a semiconductor device comprising the steps of forming a first insulator film having an electrode hole therein, depositing an amorphous silicon film on the first insulator film including inside the electrode hole, forming a second insulator film on the amorphous silicon film, etching back the first insulator film and the amorphous silicon film and wet-etching the first insulator film and the second insulator film to leave a cylindrical electrode film made from the amorphous silicon film, removing an outer surface portion of the cylindrical electrode film by a specified amount, heat treating the cylindrical electrode film to form hemispherical grains thereon, and forming a capacitor including the cylindrical electrode and another electrode film.
In accordance with the present invention, the CVD silicon film or the cylindrical electrode film has a uniform phosphorous concentration, which provides a uniform grain size for the hemispherical grains formed on the CVD silicon film or the cylindrical electrode film to achieve a larger surface area of the CVD silicon film or the cylindrical electrode film. Thus, a large capacitance can be obtained from the HSG-Si structure.
REFERENCES:
patent: 5913127 (1999-06-01), Dennison et al.
patent: 6069053 (2000-05-01), Ping et al.
patent: 3-74842 (1991-03-01), None
patent: 4-45521 (1992-02-01), None
patent: 7-45529 (1995-02-01), None
patent: 7-147246 (1995-06-01), None
patent: 7-335842 (1995-12-01), None
patent: 9-219499 (1997-08-01), None
patent: 9-298284 (1997-11-01), None
Japanese Office Action dated Jan. 25, 2001, with partial English translation.
McGinn & Gibb PLLC
NEC Corporation
Nguyen Tuan H.
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