Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Of specified configuration
Reexamination Certificate
2000-04-04
2001-08-14
Everhart, Caridad (Department: 2825)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Of specified configuration
C257S774000, C438S637000, C438S640000, C438S696000
Reexamination Certificate
active
06274936
ABSTRACT:
FIELD OF THE INVENTION
The invention relates to the field of semiconductor manufacture, and more particularly to a process for forming an opening in a layer, for example in an insulator layer, to contact an underlying layer.
BACKGROUND OF THE INVENTION
To form a semiconductor device, contacts or other openings, for example in an oxide, are often formed to expose an underlying layer such as a wafer, a metal layer, a polycrystalline silicon layer, or various other layers. To protect a desirable layer such as a word line or a digit line over the layer to be exposed, an etch stop layer or a sacrificial layer is formed over the desirable layer. The sacrificial layer often comprises silicon nitride. During the removal of an oxide layer, the silicon nitride etch stop layer can also be removed albeit usually at a slower rate than the oxide removal. The erosion of the silicon nitride layer can cause problems, for example if the underlying layer is exposed and erosion begins on the underlying layer.
A process sequence which protects a desired layer more efficiently than previous process sequences would be advantageous.
SUMMARY OF THE INVENTION
A method for forming a semiconductor device comprises the steps of forming an insulation layer having first and second openings therein. The openings, by way of the inventive process, are electrically connected by an electrically conductive spacer such as polycrystalline silicon. Subsequently, a protective layer is formed in at least one of the openings to isolate the electrical connection between the first and second openings.
Objects and advantages will become apparent to those skilled in the art from the following detailed description read in conjunction with the appended claims and the attached drawings.
REFERENCES:
patent: 5114879 (1992-05-01), Madan
patent: 5146291 (1992-09-01), Watabe et al.
patent: 5264391 (1993-11-01), Son et al.
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patent: 5408130 (1995-04-01), Woo et al.
patent: 5422504 (1995-06-01), Chang et al.
patent: 5473184 (1995-12-01), Murai
patent: 5637534 (1997-06-01), Takeyasu et al.
S. Wolf, “Silicon Processing for the VLSI Era vol. 2” Lattice Press, Calif. (1990) p. 199.
Everhart Caridad
Micro)n Technology, Inc.
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